Patents by Inventor Hsi-En Liu
Hsi-En Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967959Abstract: The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.Type: GrantFiled: July 11, 2022Date of Patent: April 23, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Hsi-En Liu
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Patent number: 11868150Abstract: The present invention discloses a power supply stabilizing circuit having noise suppressing mechanism configured to drive a voltage-control oscillating circuit that includes a current-adjusting N-type transistor including a drain, a source and a gate and an adjusting voltage generation circuit. The drain receives a first operation voltage. The source generates a power signal to the voltage control oscillator circuit. The gate receives an adjusting voltage. The adjusting voltage generation circuit operates according to a second operation voltage higher than the first operation voltage and receives a reference voltage that is a division of the first operation voltage to generate the adjusting voltage. The adjusting voltage is a sum of the reference voltage and a threshold voltage of the current-adjusting N-type transistor such that the current-adjusting N-type transistor operates in a saturation region to keep a current variation amount of the power signal smaller than a predetermined value.Type: GrantFiled: June 23, 2022Date of Patent: January 9, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Hsi-En Liu
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Publication number: 20230291397Abstract: A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.Type: ApplicationFiled: February 24, 2023Publication date: September 14, 2023Inventors: Chien-Tsu YEH, Hsi-En LIU, Yi-Chun HSIEH
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Publication number: 20230291398Abstract: The present disclosure provides a signal converting circuit including a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert multiple input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal. The reference information is relevant to a change of the phase interpolator circuit due to a manufacture process variation.Type: ApplicationFiled: February 24, 2023Publication date: September 14, 2023Inventors: Chien-Tsu YEH, Hsi-En LIU, Yi-Chun HSIEH
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Publication number: 20230022377Abstract: The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.Type: ApplicationFiled: July 11, 2022Publication date: January 26, 2023Inventor: HSI-EN LIU
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Publication number: 20220413530Abstract: The present invention discloses a power supply stabilizing circuit having noise suppressing mechanism configured to drive a voltage-control oscillating circuit that includes a current-adjusting N-type transistor including a drain, a source and a gate and an adjusting voltage generation circuit. The drain receives a first operation voltage. The source generates a power signal to the voltage control oscillator circuit. The gate receives an adjusting voltage. The adjusting voltage generation circuit operates according to a second operation voltage higher than the first operation voltage and receives a reference voltage that is a division of the first operation voltage to generate the adjusting voltage. The adjusting voltage is a sum of the reference voltage and a threshold voltage of the current-adjusting N-type transistor such that the current-adjusting N-type transistor operates in a saturation region to keep a current variation amount of the power signal smaller than a predetermined value.Type: ApplicationFiled: June 23, 2022Publication date: December 29, 2022Inventor: HSI-EN LIU
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Patent number: 10819350Abstract: The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.Type: GrantFiled: November 26, 2019Date of Patent: October 27, 2020Assignee: Realtek Semiconductor Corp.Inventors: Hsi-En Liu, Shawn Min, You-Jyun Peng
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Publication number: 20200287554Abstract: The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.Type: ApplicationFiled: November 26, 2019Publication date: September 10, 2020Inventors: Hsi-En Liu, Shawn Min, You-Jyun Peng
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Patent number: 10715359Abstract: The present invention provides a decision feedback equalizer including a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit generates a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and the first latch circuit generates a first digital signal according to the first set signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit generates the second set signal and the second reset signal according to the input signal, the first set signal and the first reset signal, and the second latch circuit generates a second digital signal according to the second set signal and the second reset signal.Type: GrantFiled: February 27, 2020Date of Patent: July 14, 2020Assignee: Realtek Semiconductor Corp.Inventors: Hsi-En Liu, Shawn Min, Yi-Chun Hsieh
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Publication number: 20150341022Abstract: The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area.Type: ApplicationFiled: August 21, 2014Publication date: November 26, 2015Inventors: HSI-EN LIU, SUNG-YAU YEH
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Patent number: 9190990Abstract: The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area.Type: GrantFiled: August 21, 2014Date of Patent: November 17, 2015Assignee: ILI TECHNOLOGY CORP.Inventors: Hsi-En Liu, Sung-Yau Yeh