Abstract: A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.

Abstract: A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.

Abstract: A memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines extending in a row direction and coupled to respective rows of the memory cells, and a plurality of local bit lines extending in a column direction and coupled to respective columns of the memory cells. The control unit is configured to program a selected one of the rows of memory cells to have a predetermined pattern of digital states, couple selected ones of the local bit lines to a global bit line and couple unselected ones of the local bit lines to ground based on the predetermined pattern, apply a stress voltage to the global bit line, and after a predetermined period of time, sense the digital states of the selected row of memory cells.

Abstract: The invention provides a semiconductor wafer with a die area and a scribe area, and the semiconductor wafer includes a die and a testing circuit. The die is formed on the die region of the semiconductor wafer, and the die includes a main circuit. The testing circuit is disposed on the scribe area of the semiconductor wafer, and is electrically connected to the die for testing the main circuit.

Abstract: A resistive memory device is provided. A first cell is coupled to a word line, a first bit line and a source line. A second cell is coupled to the word line, a second bit line and the source line. A control circuit controls the levels of the word line, the first bit line and the source line to execute a set operation for the first cell and execute a reset operation for the second cell. After the set and the reset operations, the resistance of the first cell is less than the resistance of the second cell. During the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level. During the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level.

Abstract: The invention provides a semiconductor wafer with a die area and a scribe area, and the semiconductor wafer includes a die and a testing circuit. The die is formed on the die region of the semiconductor wafer, and the die includes a main circuit. The testing circuit is disposed on the scribe area of the semiconductor wafer, and is electrically connected to the die for testing the main circuit.

Abstract: A data storage device and fabrication and control methods thereof are disclosed. The data storage device includes a first-first sub-block of memory cells, a second-first sub-block of memory cells, a first well switch, a second well switch and a first group of word lines. The first well switch is operative to convey a first well bias to bias the first-first sub-block of memory cells. The second well switch is operative to convey a second well bias to bias the second-first sub-block of memory cells. Further, the first-first and the second-first sub-blocks both are activated according to the first group of word lines.

Abstract: There is disclosed a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic. The MOS transistors manufactured by the CMOS process are used as circuit components and are properly biased so as to provide the rectifying capability, and thus are used as a rectifying diode. Furthermore, with a proper bias, the rectifying diode has zero cut-in voltage and a low current loss, and thus a high efficient rectifier can be implement.

Abstract: There is disclosed a circuit for simulating zero cut-in voltage diode and a rectifier having zero cut-in voltage characteristic. The MOS transistors manufactured by the CMOS process are used as circuit components and are properly biased so as to provide the rectifying capability, and thus are used as a rectifying diode. Furthermore, with a proper bias, the rectifying diode has zero cut-in voltage and a low current loss, and thus a high efficient rectifier can be implement.

Abstract: A row decoder for a nonvolatile memory having a low-voltage power supply that minimizes the load capacitance presented to a high voltage source without requiring additional circuitry. The row decoder accomplishes this by providing a local decoder having only one input requiring a boosted voltage higher than the power supply voltage. Further, predecoders are used to reduce the number of local decoders that receive the boosted voltage.

Abstract: A voltage pump circuit includes a native MOS device coupled as a charge transfer device (M1) between input and output stage nodes. A parallel-coupled MOS pair (M2, M3) is coupled between drain (input node) and source (output node) of the charge transfer device, in which M3 is configured as a diode. A clock generator outputs at least three non-overlapping phase signals: .phi.1 (which goes high at t1 and low at t6), .phi.2 (which goes high at t3 and low at t4), .phi.3 (which goes low qt t2 and high at t5). The t1 .phi.1 positive transient is AC-coupled to M1's drain, and a smaller fraction of the transient is coupled to M1's gate, precharging M1, which begins to turn-on. The .phi.3 t2 negative transient is AC-coupled to M1's source, increasing M1 gate-source potential, which more fully turns-on M1. The .phi.2 t3 positive transient is coupled to M1's gate, turning-on M1 very hard. A phase clock generator outputting square-wave, same-frequency signals having respective 90.degree.

Abstract: A sub-bit line architecture for non-volatile memory devices. Four sub-bit lines are coupled to each main bit line. The sub-bit lines are approximately one half the length of the main bit lines in each sector. This sub-bit line length provides low parasitic capacitance and high signal integrity. Each sub-bit line is coupled to a main bit line through a select transistor. A column latch is coupled to each main bit line to provide program data. Data is programmed to the memory array in a page program mode. In page program mode, the selected sub-bit line applies a programming voltage to the memory cell transistor drain terminals. The drain voltage is applied to all of the memory cell transistor drains coupled to the selected sub-bit line. Since the sub-bit lines are only half the length of the main bit lines in each sector, the number of memory cell transistors coupled to each sub-bit line is about half the number coupled to sub-bit lines that are the length of the main bit line.

Abstract: A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling, local decoder circuitry. The local decoder includes a set of word line drivers, each of which sets the voltage level of a corresponding local word line in response to the voltage levels of its associated global word line and a collection of control signals. Each word line driver includes one p-channel transistor and two n-channel transistors. These three transistors collectively establish selected local word lines at appropriate voltages for erase, program and read operations. The three transistors also establish unselected local word lines at solid bias voltages that prevent disturbance of memory cells that are not the target of a memory operation.

Abstract: An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock terminal to the gate of the pass transistor, and a diode from the transfer stage output to ground. When the transfer stage input goes low, charge is coupled through the resistor to pre-charge the gate of the pass transistor. The resistor has a higher junction breakdown voltage than a transistor which allows the gate of the pass transistor to be driven to a larger voltage.

Abstract: The present invention is a space efficient redundant column decoder circuit for use in a non-volatile memory device. The redundant column decoder compares a n-bit stored defective address with a n-bit presented address. Based on this comparison, an output signal is generated. This output signal is used both to specify the redundant column (or set of columns) associated with the redundant column decoder circuit, and to de-activate all of the other column decoders in the device. The redundant column decoder has a pull-up path and a parallel combination of n pairs of complementary pull-down paths. The pull-up path is connected to the pull-down paths at an output node, and the output signal is taken at this output node. Each pair of complementary pull-down paths has a first pull-down path and a second pull-down path. The first pull down path has a first non-volatile memory cell in series with and connected to a first address transistor. The first address transistor is also connected to the output node.