Patents by Inventor Hsi-Ying Yuan

Hsi-Ying Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145565
    Abstract: A power chip package module and a manufacturing method thereof are provided. In the manufacturing method, a temporary carrier having an alignment pattern is provided, in which the temporary carrier includes a base and a peelable adhesive material disposed on the base. Thereafter, a circuit board having an accommodating space passing therethrough is disposed on the temporary carrier according to the alignment pattern. Furthermore, a chip is disposed in the accommodating space with an active surface thereof facing the temporary carrier according to the alignment pattern, in which the chip is fixed on the temporary carrier by the peelable adhesive material. The accommodating space is filled with a molding material to form an initial package structure. The initial package structure is separated from the temporary carrier, and then an electrically and thermally conductive layer is formed on a bottom surface of the chip and is in contact therewith.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 12, 2021
    Assignee: YOUNGTEK ELECTRONICS CORPORATION
    Inventors: Hsi-Ying Yuan, Tung-Chuan Wang, Chun-Yuan Hou, Ping-Lung Wang, Tzu-kuei Wen
  • Publication number: 20210043532
    Abstract: A power chip package module and a manufacturing method thereof are provided. In the manufacturing method, a temporary carrier having an alignment pattern is provided, in which the temporary carrier includes a base and a peelable adhesive material disposed on the base. Thereafter, a circuit board having an accommodating space passing therethrough is disposed on the temporary carrier according to the alignment pattern. Furthermore, a chip is disposed in the accommodating space with an active surface thereof facing the temporary carrier according to the alignment pattern, in which the chip is fixed on the temporary carrier by the peelable adhesive material. The accommodating space is filled with a molding material to form an initial package structure. The initial package structure is separated from the temporary carrier, and then an electrically and thermally conductive layer is formed on a bottom surface of the chip and is in contact therewith.
    Type: Application
    Filed: June 10, 2020
    Publication date: February 11, 2021
    Inventors: HSI-YING YUAN, TUNG-CHUAN WANG, CHUN-YUAN HOU, PING-LUNG WANG, Tzu-kuei Wen
  • Publication number: 20180315712
    Abstract: Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.
    Type: Application
    Filed: November 20, 2017
    Publication date: November 1, 2018
    Inventors: Sung-Lien He, Chun-Yuan Hou, Tung-Chuan Wang, Hsi-Ying Yuan, Feng-Yi Chang
  • Patent number: 10115673
    Abstract: Provided is an embedded substrate package structure, including, from top to bottom, a fourth dielectric layer, a second substrate, a chip with a fifth dielectric layer, a third dielectric layer, a second dielectric layer, a first substrate and a first dielectric layer; wherein the substrates are disposed respectively with wire layers and through holes, and each of dielectric layers is disposed with openings, conductive bumps or conductive pads, wire layers, through holes, and chip to collectively form electrical connection. The chip is electrically connected to the substrate in a flip-chip manner, and the back of the chip interfaces a dielectric layer. Compared to the prior art which chip bonding is in face-up mode, the packaging structure with the face-down chip of the present invention can simplify the manufacturing process by the flip-chip method.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 30, 2018
    Inventors: Sung-Lien He, Chun-Yuan Hou, Tung-Chuan Wang, Hsi-Ying Yuan, Feng-Yi Chang
  • Publication number: 20180166390
    Abstract: Provided is a planar package structure and its manufacturing method. The planar package structure totally packages a die to make the die unexposed and to protect the die from impact or scratch. Further, at least one conductive pad of the die is electronically connected to an external electronic circuit through a plurality of wiring patterns and through holes filled with conductive materials. Then, the die may be connected to the external electronic circuit and may be protected from impact or scratch.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Chao-Ching Yu, Lin-Ta Chung, Hsi-Ying Yuan, Tung-Chuan Wang
  • Patent number: 9810662
    Abstract: The present invention provides a structure for integrating microfluidic devices and electrical biosensors, including: a substrate for carrying an electrical biosensor; a microfluidic channel layer for providing at least a fluid to flow; a cover member for the inflow and outflow of the at least a fluid, and an electrical biosensor, having a biosensing layer and mounted to the cover member in a flip-chip manner; wherein the fluid flows into an inlet, passes the electrical biosensor for sensing and flows out through a fluid outlet.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 7, 2017
    Assignees: CHIP WIN TECHNOLOGY CO., LTD.
    Inventors: Chao-Ching Yu, Lin-Ta Chung, Hsi-Ying Yuan, Ke-Pan Liao
  • Publication number: 20170282186
    Abstract: The present invention provides a structure for integrating microfluidic devices and optical biosensors, including: a holder member for carrying and receiving an optical biosensor; microfluidic channel layer for providing at least a fluid to flow; and a cover member for the inflow and outflow of the at least a fluid, the at least a fluid flowing from an inlet, passing the optical biosensor by at least a fluid channel for sensing, and then flowing out through at least one fluid outlet. As such, the integrating structure of the present invention can detect the optical signal produced by the optical biosensor, transport fluid, and avoid leakage, and is applicable to the integration of various forms of optical biosensors and microfluidic devices.
    Type: Application
    Filed: November 16, 2016
    Publication date: October 5, 2017
    Inventors: CHAO-CHING YU, LIN-TA CHUNG, HSI-YING YUAN, KE-PAN LIAO
  • Patent number: 7476565
    Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 13, 2009
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Wen-Bin Sun, Hsi-Ying Yuan, Chun Hui Yu
  • Publication number: 20080044945
    Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.
    Type: Application
    Filed: May 3, 2007
    Publication date: February 21, 2008
    Inventors: Wen-Kun Yang, Wen-Bin Sun, Hsi-Ying Yuan, Chun Hui Yu