Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Abstract: A bracket module and a computing device including the bracket module are disclosed. The bracket module includes a housing structure. The housing structure includes a plurality of slots. Each slot is configured to accept a device inserted therein. The housing structure is configured for attachment in a chassis of the computing device. The bracket module further includes a tray structure. The tray structure includes a fixed end connected to the housing structure and a free end opposite from the fixed end. The tray structure is configured to rotate relative to the housing structure about the fixed end. The bracket module further includes at least one fastener configured to engage the tray structure with the housing structure in an open position.

Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A conveying unit includes a housing; a collision prevention mechanism disposed on a sidewall of the housing; a gripping member configured to hold a carrier for carrying a semiconductor structure; a sensor disposed on the gripping member and configured to measure and collect data associated with vibration of the gripping member; and an unit controller disposed on the gripping member and configured to analyze the data from the sensor and control a movement of the conveying unit.

Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.

Abstract: A method for operating a conveying system is provided. An overhead hoist transport (OHT) vehicle is provided, wherein the OHT vehicle includes a gripping member configured to grip and hold a carrier, and a receiver configured to receive a signal. The signal is transmitted to the receiver of the OHT vehicle. The OHT vehicle is moved toward the carrier, and the carrier is gripped by the gripping member of the OHT vehicle. A lifting force is determined based on a weight of a carrier, a number of workpieces in the carrier, or a vertical distance between the OHT vehicle and the carrier, and the lifting force is applied to the carrier.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain, A TFT is also provided.

Abstract: A thin film transistor is provided. The thin film transistor disposed on a substrate includes a gate electrode, a gate dielectric layer, a patterned semiconductor layer, a source electrode, a drain electrode covered with an anticorrosive conductive layer, a patterned passivation layer and a transparent conductive layer. The anticorrosive conductive layer includes indium tin oxide or indium zinc oxide, and is used to prevent the drain electrode from being over etched during the process of etching the passivation layer. A method for manufacturing the thin film transistor is also provided herein.

Abstract: An apparatus that is capable of outputting spatial information of a device component is disclosed. The apparatus includes a storage unit, a processing unit, and an output unit. The storage unit stores a component model file. The processing unit receives an accessing command which includes a reference data of the device component. The processing unit reads the component model file corresponding to the reference data according to the accessing command, and the component model file is then outputted by the output unit. Specifically, the outputted component model file includes a two-dimensional (2D) paper-based image file, which could be folded into a corresponding three-dimensional (3D) model. It is worth noting that the size of 3D model is substantially equal to the actual size of the device component represented by the 3D model.

Abstract: In a snap-in fan seat and heat sink, the fan seat is provided for latching a cooling body having a notch formed on both sides of the cooling body separately, and the fan seat includes a seat body installed onto a side of the heat sink, a buckle separately and pivotally coupled to both opposite sides of the seat body, a buffer unit installed to the seat body and at a position proximate to a side of the heat sink and pressed against the heat sink, and each buckle includes a hook plate latched into the notch for mounting a fan onto the seat body, and then the seat body is latched onto the cooling body to constitute the heat sink, so as to simplify the way of assembling the fan seat and the cooling body and enhance the convenience of use.

Abstract: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut after etching due to different materials in the multilayer structure or the interface effect.

Abstract: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode is provided. The gate is disposed over a substrate, wherein the gate comprises at least one layer of aluminum-yttrium alloy nitride. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source electrode and the drain electrode are disposed over the semiconductor layer.

Abstract: A plasma sputtering target assembly and a method therefor are provided. The sputtering target assembly includes a target, a bonding layer having a plurality of particles and having a first side bonded with the target and second side, and a backplate bonded with the second side of the bonding layer. The particles are being provided when the backplate is heated. Alternatively, a plurality of protrusions is formed on the backplate and the bonding layer is larger than or equal to the protrusions in altitude. Since the bonding layer has a composition and sputter yield of the part different from that of the target, in sputtering, the bonding layer is made exposed to plasma and thus an exceptional discharging phenomenon is caused when the target is struck through. By detecting the phenomenon, whether the target is almost over-sputtered may be forecasted and the backplate may be prevented from being struck through.

Abstract: A semiconductor device and its manufacturing method are disclosed. The nitrogen flow is gradually changed to form a semiconductor device with a gate or a source/drain having a nitrified gradient layer structure. Different extents of nitrification inside the nitrified gradient layer structure provide protection and buffering to prevent the undercut after etching due to different materials in the multilayer structure or the interface effect.