Abstract: A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A display device includes: a substrate; a metal layer disposed on the substrate; an insulating layer disposed on the metal layer; and a first light emitting diode including a first electrode disposed on the metal layer, wherein a via hole passes through the insulating layer, the first electrode electrically connects to the metal layer through the via hole, and an outline of the via hole includes an arc edge.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.

Abstract: Disclosed are HfO2—ZrO2 superlattice heterostructures such as a gate stack (24), stabilized with mixed ferroelectric-antiferroelectric order. directly integrated onto silicon (Si) transistors and scaled down to ˜20 ?. the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is ˜6.5 ? effective SiO2 thickness, which is even smaller than the interfacial SiO2 thickness (8.0-8.5 ?) itself. and the resulting large capacitance cannot be achieved in conventional HfO2-based high-? dielectric gate stacks without scavenging the interfacial SiO2. which has adverse effects on the electron transport and gate leakage current. Accordingly. the disclosed gate stacks (24), which do not require such scavenging.

Abstract: Techniques pertaining to anti-motion and anti-interference frame exchange sequences in wireless communications are described. A station (STA), such as a Wi-Fi equipment, determines to enable a frame exchange sequence (FES). The STA then communicates with one or more other STAs by utilizing the FES in which preamble puncturing sounding and data transmission are performed in a same transmission opportunity (TXOP).

Abstract: An electronic device is provided. The electronic device includes a first substrate, a polarizer, and a conductive adhesive. The polarizer is disposed on the first substrate and has a conductive layer. The conductive adhesive is disposed on the first substrate and electrically connected to the conductive layer. From a top view, the conductive adhesive is adjacent to an edge of the polarizer and has an extending direction. An angle between the extending direction and an absorption-axis direction of the polarizer is between 80° and 100°.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Abstract: An automated beverage preparation apparatus includes: multiple pumps for extracting multiple fluid materials stored in multiple material containers, and pushing the extracted fluid materials to move forward; a fluid output device coupled with the multiple pumps and arranged to operably dispense fluid materials to a beverage container; a user control interface arranged to operably generate a control command; a processing circuit arranged to operably generate a corresponding control signal according to the control command; and a pump control circuit arranged to operably control the multiple pumps according to the control signal. The pump control circuit conducts a layered drink making operation under control of the processing circuit to cause the fluid output device to dispense different fluid materials to the beverage container, so as to automatically form a layered drink/gradient drink having at least two color layers within the beverage container.

Abstract: An automated beverage preparation apparatus includes: multiple pumps for extracting multiple fluid materials stored in multiple material containers, and pushing the extracted fluid materials to move forward; a fluid output device coupled with the multiple pumps and arranged to operably dispense fluid materials to a beverage container; a user control interface arranged to operably generate a control command; a processing circuit arranged to operably generate a corresponding control signal according to the control command; and a pump control circuit arranged to operably control the multiple pumps according to the control signal. The pump control circuit conducts a sparkling drink making operation under control of the processing circuit to cause the fluid output device to dispense different fluid materials to the beverage container in order, so as to automatically form a sparkling drink/aerated drink with a predetermined flavor within the beverage container.

Abstract: Examples pertaining to preamble puncturing negotiation in wireless communications are described. A station (STA) may receive a control frame, and, in response, apply the MRU pattern for one or more transmissions or receptions in a transmission opportunity (TXOP). In the control frame, either a plurality of first reserved bits in a SERVICE field or a plurality of bits in a User Info field are set to indicate a multiple resource unit (MRU) pattern regarding preamble puncturing.

Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

Abstract: Disclosed is an electronic device including a tunable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the tunable element. The first power supply circuit drives the tunable element during a first time period. The second power supply circuit drives the tunable element during a second time period.

Abstract: A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

Abstract: Methods and apparatus are provided for UE-triggered handover and early preparation with coexistence of the network-triggered handover. In one novel aspect, the UE is configured early measurement report configuration, receives an early handover command from the serving base station with a handover candidate cell list, monitors handover triggering conditions for each candidate cell on the handover candidate cell list based on a UE-triggered handover configuration and performs the UE-triggered handover to a candidate cell when the corresponding triggering condition is met for the candidate cell. In one embodiment, the UE receives a network-triggered handover command to a target cell, suspends the UE-triggered handover configuration and performs the network-triggered handover to the target cell. The UE discards the UE-triggered handover configuration upon success of the network-triggered handover and resumes the UE-triggered handover configuration upon failure of the network-triggered handover.

Abstract: An exercise device is providing, including: a frame, including a weighting seat, two first movable pulley assemblies and two second movable pulley assemblies; a first operation assembly, disposed on the frame, including two first connecting members connected to opposing ends of the first cable and a first cable curving back around the two first movable pulley assemblies and the weighting seat; a second operation assembly, including two second connecting members and two second cables each being connected to the frame and curving back around one first movable pulley assembly and one second movable pulley assembly, each second connecting members being connected to one second cable; a third operation assembly, including two third connecting members and two third cables each being connected to the frame and curving back around one second movable pulley assembly, each third connecting members being connected to one third cable.

Abstract: An air valve structure arranged on a base comprises an air plug and a state-switching component. The air plug is arranged in an air chamber in an axial direction. The air plug includes a closing state to close the air hole, and an opening state to open the air hole. The state-switching component comprises a driving member that links the air plug, a shape-memory alloy (SMA) wire connected with the driving member, and at least one conductive member connected with the SMA wire. The driving member exerts an acting force to the air plug based on a condition of electricity provided by the conductive member for the SMA wire. The direction of the acting force is non-parallel with the axial direction and the air plug is moved and changed between the closing state and the opening state by the acting force.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.