Abstract: The present disclosure provides a method for fabricating an image sensor. The method includes the following operations. A cavity is formed at a first surface of a substrate. A germanium layer is formed in the cavity. A first heavily doped region is formed in the germanium layer by an implantation operation. A second heavily doped region is formed at a position proximal to a top surface of the germanium layer, wherein the second heavily doped region is laterally surrounded by the first heavily doped region from a top view perspective. An interconnect structure is formed over the germanium layer.

Abstract: The present invention provides a memory controller including a decoder, an error bit counter and a refresh rate control circuit. The decoder is configured to receive and decode data from a memory module to generate decoded data. The error counter is coupled to the decoder, and is configured to generate error bit information of the data. The refresh rate control circuit is coupled to the error counter, and is configured to determine a refresh rate of the memory module according to the error bit information.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip that includes interface circuits and a control circuit. The interface circuits is configured to interface the IC chip to buses that couple the IC chip with a memory chip, to drive signals onto the buses for transmission to the memory chip and to receive signals that are transmitted on the buses from the memory chip. The control circuit is configured to receive a ratio change of transmission rates for command signals and data signals, control the interface circuits to transmit information signals to the memory chip to inform the ratio change, configure the interface circuits according to the ratio change, and allow the interface circuits to start transmit/receive signals according to the ratio change at a time.

Abstract: A refresh control method for a memory system is provided. The memory system includes a dynamic random access memory with a register set and a memory cell array. The refresh control method includes the following steps. Firstly, a masking command or an unmasking command is issued, and thus the register set is updated. A first region of the memory cell array is set as a masked region according to the masking command. A second region of the memory cell array is set as an unmasked region according to the unmasking command. Then, a refresh command is issued to the dynamic random access memory. According to the refresh command, a refresh action is performed on the second region of the memory cell array.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip that includes interface circuits and a control circuit. The interface circuits is configured to interface the IC chip to buses that couple the IC chip with a memory chip, to drive signals onto the buses for transmission to the memory chip and to receive signals that are transmitted on the buses from the memory chip. The control circuit is configured to receive a ratio change of transmission rates for command signals and data signals, control the interface circuits to transmit information signals to the memory chip to inform the ratio change, configure the interface circuits according to the ratio change, and allow the interface circuits to start transmit/receive signals according to the ratio change at a time.

Abstract: An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.

Abstract: An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.

Abstract: An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.

Abstract: A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.

Abstract: An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.

Abstract: A digital television, a memory controller and a method for controlling access of a memory device are provided. The digital television comprises the memory device and the memory controller. The memory controller comprises a storage buffer and a clock adjustment device. The storage buffer buffers a data read from the memory device according to a reference clock source. The clock adjustment device provides the reference clock source and determines whether to adjust the reference clock source in response to the data. The method comprises steps of: providing a reference clock source; buffering a data read from the memory device according to the reference clock source; and determining whether to adjust the reference clock source in response to the data.

Abstract: A memory controller and a method for data access are provided. The memory controller writes a data packet to or reads a data packet from a memory. The memory controller comprises a first register, a second register, a data packet adjuster, and a burst length determination unit. The first register stores a data bus width. The second register stores an operating frequency of the memory controller. The burst length determination unit determines a burst length according to the operating frequency. The data packet adjuster adjusts the data packet according to the data bus width and the burst length.

Abstract: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.

Abstract: A memory controller for a memory device. The memory controller includes a first sensor, a second sensor, and a command generator. The first sensor detects an operating environment of the memory controller. The second sensor detects an operating status of the memory controller. The command generator is coupled to the first sensor, the second sensor, and the memory device, and facilitates the sending of commands to the memory device to calibrate the memory device when the operating environment detected by the first sensor meets a first prerequisite, and the operating status detected by the second sensor meets a second prerequisite.

Abstract: A memory control method, a memory controller, and a memory device implementing the method are provided. The memory controller controls the memory device comprising a plurality of banks, and a first row in a bank is activated for access. The memory controller receives a request for access of a second row in the bank and delivers a special command to the memory device. The memory device deactivates the first row and activates the second row upon receipt of the special command.

Abstract: A digital television system, a memory controller, and a method for data access are provided. The digital television system comprises a memory and the memory controller. The memory controller writes a data packet to or reads a data packet from the memory. The memory controller comprises a register, a data packet adjuster, a burst length determination unit, and a frequency determination unit. The register sets a data bus width. The data packet adjuster adjusts the data packet according to the data bus width. The burst length determination unit determines a burst length according to the data bus width. The frequency determination unit determines an operating frequency of the memory controller according to the data bus width. The memory controller writes or reads the adjusted data packet in response to the burst length and the operating frequency.

Abstract: A memory control method, a memory controller, and a memory device implementing the method are provided. The memory controller controls the memory device comprising a plurality of banks, and a first row in a bank is activated for access. The memory controller receives a request for access of a second row in the bank and delivers a special command to the memory device. The memory device deactivates the first row and activates the second row upon receipt of the special command.

Abstract: A memory controller includes a first data converter for converting incoming data into a first data in which a bit width of the incoming data and a bit width of the first data corresponds to a first ratio; a second data converter for converting the incoming data into a second data where the bit width of the incoming data and a bit width of the second data corresponds to a second ratio; and a first selector, coupled to the first and second data converters, for outputting either the first data or the second data to a memory device according to a memory mode setting.

Abstract: A memory controller for a memory device. The memory controller includes a first sensor, a second sensor, and a command generator. The first sensor detects an operating environment of the memory controller. The second sensor detects an operating status of the memory controller. The command generator is coupled to the first sensor, the second sensor, and the memory device, and facilitates the sending of commands to the memory device to calibrate the memory device when the operating environment detected by the first sensor meets a first prerequisite, and the operating status detected by the second sensor meets a second prerequisite.

Abstract: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.