Patents by Inventor Hsiao-Kang Chang
Hsiao-Kang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240162084Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: ApplicationFiled: January 26, 2024Publication date: May 16, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen HUANG, Ting-Ya LO, Shao-Kuan LEE, Chi-Lin TENG, Cheng-Chin LEE, Shau-Lin SHUE, Hsiao-Kang CHANG
-
Publication number: 20240088023Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
-
Publication number: 20240087980Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.Type: ApplicationFiled: February 17, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Yen-Pin HSU, Li-Ling SU, Ming-Hsien LIN, Hsiao-Kang CHANG
-
Patent number: 11923243Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang
-
Publication number: 20240038528Abstract: A method for manufacturing a semiconductor structure includes: forming a dielectric layer on a base structure; forming a trench in the dielectric layer to expose the base structure; forming a metal contact in the trench; and performing a plurality of first atomic layer deposition (ALD) cycles to form a plurality of first atomic layers which cover the dielectric layer and the metal contact and which serve as an etch stop layer. Each of the first ALD cycles includes: forming a corresponding one of the first atomic layers; and performing a treatment to convert the corresponding first atomic layer into monocrystalline phase at a temperature not greater than 425° C.Type: ApplicationFiled: July 28, 2022Publication date: February 1, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Hsiao-Kang CHANG
-
Publication number: 20240038666Abstract: A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes a dielectric layer, an interconnect structure disposed in the dielectric layer, and an etch stop layer which is disposed on a lower end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of SixCyNz, wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Cheng-Chin LEE, Yen-Ju WU, Hsin-Yen HUANG, Hsiao-Kang CHANG
-
Publication number: 20240038665Abstract: An interconnection structure is provided to include an interlayer dielectric (ILD) layer that is disposed over a substrate, a metal via that is disposed in the ILD layer, and a metal wire that is disposed over the metal via in the ILD layer and that is electrically connected to the metal via. The ILD layer includes silicon carbon nitride.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Hsiao-Kang CHANG
-
Publication number: 20240038586Abstract: A semiconductor structure includes a base structure, a plurality of electrically conductive features disposed on the base structure, and an isolation structure disposed on the base structure. The base structure includes a substrate. The electrically conductive features are spaced apart from each other. The isolation structure includes a first inter-metal dielectric feature extending horizontally to interconnect the electrically conductive features, a first air gap layer disposed in the isolation structure and around the electrically conductive features, and a first sustaining feature extending horizontally to interconnect the electrically conductive features and disposed between the first inter-metal dielectric feature and the first air gap layer. Methods for manufacturing the semiconductor structure are also disclosed.Type: ApplicationFiled: July 28, 2022Publication date: February 1, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Hsiao-Kang CHANG
-
Patent number: 11854963Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: GrantFiled: June 12, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Kuan Lee, Kuang-Wei Yang, Cherng-Shiaw Tsai, Cheng-Chin Lee, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
-
Patent number: 11848198Abstract: A method for manufacturing a semiconductor device having a low-k carbon-containing dielectric layer includes: depositing a low-k carbon-containing dielectric material, which has a carbon content ranging from 16 atomic % to 23 atomic %, using a precursor mixture to form a carbon-containing dielectric layer having a k value ranging from 2.8 to 3.3 and a porosity ranging from 0.03% to 1.0%; forming the carbon-containing dielectric layer into a patterned carbon-containing dielectric layer having a recess therein by etching, the patterned carbon-containing dielectric layer having a porosity ranging from 1.0% to 2.0%; and filling the recess with an electrically conductive material to form an electrically conductive feature in the patterned carbon-containing dielectric layer.Type: GrantFiled: August 30, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang Cheng, Ting-Ya Lo, Hsiao-Kang Chang
-
Publication number: 20230290705Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.Type: ApplicationFiled: March 14, 2022Publication date: September 14, 2023Inventors: Cheng-Chin LEE, Shau-Lin SHUE, Shao-Kuan LEE, Hsiao-Kang CHANG, Cherng-Shiaw TSAI, Kai-Fang CHENG, Hsin-Yen HUANG, Ming-Hsien LIN, Chuan-Pu CHOU, Hsin-Ping CHEN, Chia-Tien WU, Kuang-Wei YANG
-
Publication number: 20230260867Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.Type: ApplicationFiled: April 21, 2023Publication date: August 17, 2023Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Shau-Lin Shue, Hsiao-Kang Chang, Cherng-Shiaw Tsai
-
Publication number: 20230260831Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Cherng-Shiaw TSAI, Shao-Kuan LEE, Kuang-Wei YANG, Gary LIU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
-
Publication number: 20230253286Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
-
Publication number: 20230178427Abstract: An interconnection structure is provided. The interconnection structure includes an etching-process-free first dielectric layer, a first conductive structure extending within the first dielectric layer, a second dielectric layer formed under the first dielectric layer, and a second conductive structure extending through both the first dielectric layer and the second conductive layer.Type: ApplicationFiled: February 7, 2023Publication date: June 8, 2023Inventors: Cheng-Chin LEE, Ting-Ya LO, Hsiao-Kang CHANG, Hsin-Yen HUANG, Shau-Lin SHUE
-
Patent number: 11658092Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.Type: GrantFiled: November 13, 2020Date of Patent: May 23, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
-
Patent number: 11640928Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.Type: GrantFiled: August 26, 2021Date of Patent: May 2, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Shau-Lin Shue, Hsiao-Kang Chang, Cherng-Shiaw Tsai
-
Publication number: 20230075725Abstract: Disclosed herein is a glass composition that includes, based on a total weight of the glass composition, 55 wt % to 64 wt % of SiO2, 15 wt % to 22 wt % of Al2O3, 0.1 wt % to 4 wt % of CaO, 2.1 wt % to 10 wt % of MgO, 0 wt % to 8 wt % of ZnO, greater than 0 wt % and less than 7 wt % of CuO, and greater than 13.1 wt % and less than 18 wt % of B2O3. Also disclosed herein are a glass fiber and a glass article including the glass composition.Type: ApplicationFiled: September 1, 2022Publication date: March 9, 2023Inventors: Hsien-Chung HSU, Bih-Cherng CHERN, Hsiao-Kang CHANG, Chih-Yuan CHANG, Wen-Ho HSU
-
Publication number: 20230066284Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Shau-Lin Shue, Hsiao-Kang Chang, Cherng-Shiaw Tsai
-
Publication number: 20230066228Abstract: A method for manufacturing a semiconductor device having a low-k carbon-containing dielectric layer includes: depositing a low-k carbon-containing dielectric material, which has a carbon content ranging from 16 atomic % to 23 atomic %, using a precursor mixture to form a carbon-containing dielectric layer having a k value ranging from 2.8 to 3.3 and a porosity ranging from 0.03% to 1.0%; forming the carbon-containing dielectric layer into a patterned carbon-containing dielectric layer having a recess therein by etching, the patterned carbon-containing dielectric layer having a porosity ranging from 1.0% to 2.0%; and filling the recess with an electrically conductive material to form an electrically conductive feature in the patterned carbon-containing dielectric layer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Ting-Ya LO, Hsiao-Kang CHANG