Patents by Inventor Hsiao-Wen Lee

Hsiao-Wen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797007
    Abstract: The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over the second insulation, a first conductor proximal to a boundary between the first insulation and the second insulation, and an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation. A coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiao-Wen Lee, Hsiu-Mei Yu
  • Patent number: 10763239
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 10750070
    Abstract: A light-emitting diode (LED) includes s a substrate, a LED chip, and an optical lens. The LED chip is fixedly mounted to the substrate for emitting a light beam. The optical lens is mounted to the substrate and covers the LED chip. The optical lens has a light exit surface, which directs the light beam from the LED chip to travel in a direction along an optical axis to form a non-symmetric light shape. Also disclosed is a surveillance camera device that uses the LED. As such, the drawback of a conventional surveillance camera being incapable of acquiring an excellent image due to light source being overly concentrated can be eliminated.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: August 18, 2020
    Assignee: Ligitek Electronics Co., Ltd.
    Inventors: Hsiao-Wen Lee, I-Hsin Tung
  • Publication number: 20200135661
    Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.
    Type: Application
    Filed: December 31, 2019
    Publication date: April 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Wen LEE, Hsien-Wen LIU, Shin-Puu JENG
  • Patent number: 10529671
    Abstract: Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Wen Lee, Hsien-Wen Liu, Shin-Puu Jeng
  • Publication number: 20190317390
    Abstract: A structured light projection system including a substrate, a semiconductor laser chip, a first optical module, and a second optical module is provided. The semiconductor laser chip is electrically connected to the substrate. The first optical module is disposed on the substrate. The second optical module is disposed on the first optical module. The deviation rate between optical axes of the optical modules and the semiconductor laser chip and the calibration time thereof are reduced by the first optical module directly packaging the substrate through a primary optics design, so as to increase the yield of the structured light projection.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 17, 2019
    Applicant: LIGITEK ELECTRONICS CO., LTD.
    Inventors: Hsiao-Wen Lee, I-Hsin Tung
  • Publication number: 20190312963
    Abstract: An internet phone system includes an internet phone main body, an expansion device and a multiple-layer connecting card. The internet phone main body includes a first connecting port. The at least one expansion device includes a second connecting port. One end of the multiple-layer connecting card is connected to the first connecting port, and the other end is connected to the second connecting port such that the internet phone main body can be electrically connected to the expansion device via the multiple-layer connecting card. The expansion device is capable of combining with another expansion device by another multiple-layer connecting card.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Yu-Ti KUO, Wen-Hsieh HSIEH, Chao-Tang CHIU, Chien-Yi LEE, Hsiao-Wen LEE, Ching-Jen WANG
  • Patent number: 10397385
    Abstract: An internet phone system includes an internet phone main body, at least one expansion device and at least one multiple-layer connecting card. The internet phone main body includes a first connecting port. The at least one expansion device includes a second connecting port. One end of the multiple-layer connecting card is connected to the first connecting port, and the other end is connected to the second connecting port such that the internet phone main body can be electrically connected to the expansion device via the multiple-layer connecting card.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: August 27, 2019
    Assignee: PEGATRON CORPORATION
    Inventors: Yu-Ti Kuo, Wen-Hsieh Hsieh, Chao-Tang Chiu, Chien-Yi Lee, Hsiao-Wen Lee, Ching-Jen Wang
  • Publication number: 20190237405
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Application
    Filed: April 8, 2019
    Publication date: August 1, 2019
    Inventors: Han-Ping PU, Hsiao-Wen LEE
  • Publication number: 20190164912
    Abstract: The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over the second insulation, a first conductor proximal to a boundary between the first insulation and the second insulation, and an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation. A coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 30, 2019
    Inventors: HSIAO-WEN LEE, HSIU-MEI YU
  • Publication number: 20190131273
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 10269720
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Ping Pu, Hsiao-Wen Lee
  • Publication number: 20180166396
    Abstract: Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.
    Type: Application
    Filed: July 3, 2017
    Publication date: June 14, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen LEE, Hsien-Wen LIU, Shin-Puu JENG
  • Publication number: 20180145032
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 24, 2018
    Inventors: Han-Ping PU, Hsiao-Wen LEE
  • Patent number: 9899443
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen Lee, Kazuaki Hashimoto, Kuo-Chung Yee
  • Patent number: 9899563
    Abstract: A light emitting diode (LED) with a micro-structure lens includes a LED die and a micro-structure lens. The micro-structure lens includes a convex lens portion, at least one concentric ridge structure surrounding the convex lens portion, and a lower portion below the convex lens portion and the at least one concentric ridge structure. The lower portion is arranged to be disposed over the LED die. A first optical path length from an edge of the LED die to a top center of the microstructure lens is substantially the same as a second optical path length from the edge of the LED die to a side of the micro-structure lens.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: February 20, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Hsiao-Wen Lee, Shang-Yu Tsai, Pei-Wen Ko
  • Publication number: 20180026067
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 25, 2018
    Inventors: Hsiao-Wen Lee, Kazuaki Hashimoto, Kuo-Chung Yee
  • Publication number: 20170302834
    Abstract: A light-emitting diode (LED) includes s a substrate, a LED chip, and an optical lens. The LED chip is fixedly mounted to the substrate for emitting a light beam. The optical lens is mounted to the substrate and covers the LED chip. The optical lens has a light exit surface, which directs the light beam from the LED chip to travel in a direction along an optical axis to form a non-symmetric light shape. Also disclosed is a surveillance camera device that uses the LED. As such, the drawback of a conventional surveillance camera being incapable of acquiring an excellent image due to light source being overly concentrated can be eliminated.
    Type: Application
    Filed: July 5, 2017
    Publication date: October 19, 2017
    Inventors: HSIAO-WEN LEE, I-HSIN TUNG
  • Publication number: 20170175974
    Abstract: Disclosed is an illumination module for creating lateral rectangular illumination window which includes a substrate, at least one light-emitting element, and an optical lens. The light-emitting element is mounted on the substrate for generating visible light or invisible light, and having an optical axis. The optical lens is arranged on the substrate to cover the light-emitting element. The optical lens includes a light-entrance surface and a light-exiting surface opposite to the entrance surface, and the light-exiting surface has a light emission center. The light-exiting surface of the optical lens can be configured to direct a beam of light generated by the light-emitting element to output along the optical axis and pass through the light emission center to create a lateral rectangular illumination window. Whereby, the components of a camera can be reduced, and image distortion caused by compressing and converting can be prevented.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: HSIAO-WEN LEE, I-HSIN TUNG
  • Publication number: 20170180525
    Abstract: An internet phone system includes an internet phone main body, at least one expansion device and at least one multiple-layer connecting card. The internet phone main body includes a first connecting port. The at least one expansion device includes a second connecting port. One end of the multiple-layer connecting card is connected to the first connecting port, and the other end is connected to the second connecting port such that the internet phone main body can be electrically connected to the expansion device via the multiple-layer connecting card.
    Type: Application
    Filed: September 14, 2016
    Publication date: June 22, 2017
    Inventors: Yu-Ti KUO, Wen-Hsieh HSIEH, Chao-Tang CHIU, Chien-Yi LEE, Hsiao-Wen LEE, Ching-Jen WANG