Patents by Inventor Hsiao-Yen Lee
Hsiao-Yen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240088023Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
-
Patent number: 11923243Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang
-
Patent number: 11806710Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.Type: GrantFiled: June 4, 2020Date of Patent: November 7, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao-Yen Lee, Ying-Te Ou, Chin-Cheng Kuo, Chung Hao Chen
-
Patent number: 11769712Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.Type: GrantFiled: May 28, 2021Date of Patent: September 26, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao-Yen Lee, Hung-Yi Lin
-
Publication number: 20220384308Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao-Yen LEE, Hung-Yi LIN
-
Publication number: 20210379590Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao-Yen LEE, Ying-Te OU, Chin-Cheng KUO, Chung Hao CHEN
-
Publication number: 20180122749Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.Type: ApplicationFiled: November 1, 2016Publication date: May 3, 2018Inventors: Ying-Chih LEE, Chin-Cheng KUO, Yung-Hui WANG, Wei-Hong LAI, Chung-Ting WANG, Hsiao-Yen LEE
-
Patent number: 9204557Abstract: An environmental sensitive electronic device package including a first substrate, a second substrate, an environmental sensitive electronic device, gas barrier structures, micro-structures, and a filler layer is provided. The second substrate is located above the first substrate. The environmental sensitive electronic device is located on the first substrate. The gas barrier structures may be located between the first substrate and the second substrate and surround the environmental sensitive electronic device. The gas barrier structures have a first height. The micro-structures may be located between the first substrate and the second substrate and have a second height. A ratio of the second height to the first height ranges from 1/250 to 1/100. The filler layer may be located between the first substrate and the second substrate and covers the gas barrier structures and the environmental sensitive electronic device.Type: GrantFiled: November 7, 2013Date of Patent: December 1, 2015Assignee: Industrial Technology Research InstituteInventors: Hsiao-Yen Lee, Yu-Yang Chang, Pao-Ming Tsai
-
Publication number: 20140160705Abstract: An environmental sensitive electronic device package including a first substrate, a second substrate, an environmental sensitive electronic device, gas barrier structures, micro-structures, and a filler layer is provided. The second substrate is located above the first substrate. The environmental sensitive electronic device is located on the first substrate. The gas barrier structures may be located between the first substrate and the second substrate and surround the environmental sensitive electronic device. The gas barrier structures have a first height. The micro-structures may be located between the first substrate and the second substrate and have a second height. A ratio of the second height to the first height ranges from 1/250 to 1/100. The filler layer may be located between the first substrate and the second substrate and covers the gas barrier structures and the environmental sensitive electronic device.Type: ApplicationFiled: November 7, 2013Publication date: June 12, 2014Applicant: Industrial Technology Research InstituteInventors: Hsiao-Yen Lee, Yu-Yang Chang, Pao-Ming Tsai