Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.

Abstract: A method of growing a single crystal ingot includes growing a single crystal silicon ingot from a silicon melt in a crucible within an inner chamber, adding a volatile dopant into a feed tube, positioning the feed tube within an inner chamber at a first height relative to a surface of the melt, adjusting the feed tube within the inner chamber to a second height at a speed rate, and heating the volatile dopant to form a gaseous dopant as the feed tube is moved from the first height to the second height at the speed rate. Each of the second height and the speed rate are selected to control a vaporization rate of the volatile dopant. The method also includes introducing dopant species into the melt while growing the ingot by contacting the surface of the melt with the gaseous dopant.

Abstract: A device includes a substrate; semiconductor fins extending from the substrate; a liner layer on sidewalls of the semiconductor fins; an etch stop layer over the substrate and extending laterally from a first portion of the liner layer on a first one of the semiconductor fins to a second portion of the line layer on a second one of the semiconductor fins; an isolation structure over the etch stop layer, wherein the etch stop layer and the isolation structure include different materials; a gate dielectric layer over a top surface of the isolation structure; and a dielectric feature extending through the gate dielectric layer and into the isolation structure, wherein the isolation structure and the dielectric feature collectively extend laterally from the first portion of the liner layer to the second portion of the line layer.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A cup lid includes a lid body and a label placement structure. A sip hole structure and a through hole are formed at different positions on a top surface of the lid body, and the sip hole structure includes a flip-top lid, a protruding buckle formed on the flip-top lid, and a buckle groove located on one side of the flip-top lid; and the label placement structure is disposed on the top surface of the lid body, where the label placement structure includes a plurality of clamping arms protruding from the top surface of the lid body, and when a label is inserted into the label placement structure, the clamping arms clamp two sides of the label.

Abstract: A cup lid includes a lid body and a label placement structure. A sip hole structure and a through hole are formed at different positions on a top surface of the lid body, and the sip hole structure includes a flip-top lid, a protruding buckle formed on the flip-top lid, and a buckle groove located on one side of the flip-top lid; and the label placement structure is disposed on the top surface of the lid body, where the label placement structure includes a plurality of clamping arms protruding from the top surface of the lid body, and when a label is inserted into the label placement structure, the clamping arms clamp two sides of the label. In addition, a cup lid attached with a tea bag is also provided.

Abstract: A cup lid includes a lid body and a label placement structure. A sip hole structure and a through hole are formed at different positions on a top surface of the lid body, and the sip hole structure includes a flip-top lid, a protruding buckle formed on the flip-top lid, and a buckle groove located on one side of the flip-top lid; and the label placement structure is disposed on the top surface of the lid body, where the label placement structure includes a plurality of clamping arms protruding from the top surface of the lid body, and when a label is inserted into the label placement structure, the clamping arms clamp two sides of the label. In addition, a cup lid attached with a tea bag is also provided.

Abstract: A layout design for I/O cell area/bond pad area interfaces, and a method of form the same, comprising: a substrate having an I/O cell area and a bond pad area separated by a trench area; and multiple metal lines over the substrate. The multiple metal lines including a lowermost metal line, lower intermediate metal lines, upper intermediate metal lines and an uppermost metal line, wherein at least one of the upper intermediate metal lines includes a respective extension portion, that is contiguous with, or separate therefrom, extending into at least through the trench area.