Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A reference voltage circuit includes a first circuit including a first PN junction device and a first resistor connected in series between a power supply node and a first node, and a second resistor connected between the first node and an intermediate node, and a third resistor connected between the intermediate node and a reference voltage output node, and a second circuit including a second PN junction device connected between the power supply node and a second node and a fourth resistor connected between the second node and the intermediate node. A feedback current causes voltage across the first resistor to offset changes in voltage across the first PN junction device. A correction current is applied to boost and or sink current in the voltage reference generator to extend the operating temperature range.

Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.

Abstract: A reference voltage circuit includes a first circuit including a first PN junction device and a first resistor connected in series between a power supply node and a first node, and a second resistor connected between the first node and an intermediate node, and a third resistor connected between the intermediate node and a reference voltage output node, and a second circuit including a second PN junction device connected between the power supply node and a second node and a fourth resistor connected between the second node and the intermediate node. A feedback current causes voltage across the first resistor to offset changes in voltage across the first PN junction device. A correction current is applied to boost and or sink current in the voltage reference generator to extend the operating temperature range.

Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.

Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.

Abstract: A circuit generates a clock signal with a tunable clock period. The circuit comprises capacitors, first tuning circuitry and second tuning circuitry. The first tuning circuitry is configured to adjust the clock period with a first period tuning step based on a first parameter and the second tuning circuit is configured to adjust the clock period with a second period tuning step based on a second parameter. The first period tuning step is different than the second period tuning step.

Abstract: A circuit generates a clock signal with a tunable clock period. The circuit comprises capacitors, first tuning circuitry and second tuning circuitry. The first tuning circuitry is configured to adjust the clock period with a first period tuning step based on a first parameter and the second tuning circuit is configured to adjust the clock period with a second period tuning step based on a second parameter. The first period tuning step is different than the second period tuning step.

Abstract: An oscillator produces an oscillator output signal usable as a clock signal, otherwise as a frequency reference on an integrated circuit. The oscillator includes an RC network with a voltage-controlled element, such as a voltage-controlled resistor, voltage-controlled capacitor or a combination including a voltage-controlled resistor and voltage-controlled capacitor. Also, a tunable element having an adjustable resistance determined by a first static parameter is included in the RC network. The oscillator also includes a feedback circuit which can include a frequency-to-voltage converter. The feedback circuit generates a control signal for the voltage-controlled element. The feedback circuit includes a feedback reference circuit having a reference output determined by a second static parameter, and a loop amplifier responsive to the reference output and the oscillator output signal.

Abstract: An oscillator produces an oscillator output signal usable as a clock signal, otherwise as a frequency reference on an integrated circuit. The oscillator includes an RC network with a voltage-controlled element, such as a voltage-controlled resistor, voltage-controlled capacitor or a combination including a voltage-controlled resistor and voltage-controlled capacitor. Also, a tunable element having an adjustable resistance determined by a first static parameter is included in the RC network. The oscillator also includes a feedback circuit which can include a frequency-to-voltage converter. The feedback circuit generates a control signal for the voltage-controlled element. The feedback circuit includes a feedback reference circuit having a reference output determined by a second static parameter, and a loop amplifier responsive to the reference output and the oscillator output signal.

Abstract: A current mirror circuit includes a current source for generating a reference current, a mirror circuit having a first node for passing a first mirroring current and a second node for passing a second mirroring current, a feedback circuit coupled to the mirror circuit for equalizing voltages on the first and second nodes, and a tunable element coupled to the mirror circuit and driven by an output of the feedback circuit for providing a target output current.

Abstract: A current mirror circuit includes a current source for generating a reference current, a mirror circuit having a first node for passing a first mirroring current and a second node for passing a second mirroring current, a feedback circuit coupled to the mirror circuit for equalizing voltages on the first and second nodes, and a tunable element coupled to the mirror circuit and driven by an output of the feedback circuit for providing a target output current.

Abstract: A method and a circuit for generating a clock signal from a clock integrated circuit are introduced herein. A compensation voltage is generated according to a temperature coefficient of a resistor and a clock period of a clock circuit, where the compensation voltage is resistor-corner independent. The clock period of the clock circuit is determined by the resistor and at least one capacitor of the clock circuit. The temperature dependence of the clock period of the clock circuit is reduced according to the compensation voltage.

Abstract: A method and a circuit for generating a clock signal from a clock integrated circuit are introduced herein. A compensation voltage is generated according to a temperature coefficient of a resistor and a clock period of a clock circuit, where the compensation voltage is resistor-corner independent. The clock period of the clock circuit is determined by the resistor and at least one capacitor of the clock circuit. The temperature dependence of the clock period of the clock circuit is reduced according to the compensation voltage.

Abstract: A regulator comprises an amplifier, a bias circuit, and a current trimming circuit. The bias circuit is coupled to the amplifier and supplies a first bias current to the amplifier in a first mode of a system including the regulator. The current trimming circuit is coupled to the bias circuit to adjust the first bias current.

Abstract: A voltage regulator, alternatively operating in an active mode in response to an enabled mode indication signal, and operating in a standby mode in response to the disabled mode indication signal, is provided. The voltage regulator comprises a regulation unit and a feedback circuit. The regulation unit drives an output node with an output signal. The feedback circuit comprises a first resistance unit, connected between the output node and the feedback node, and a second resistance unit. The second resistance unit is connected between the feedback node and a ground reference voltage, and the resistance thereof is scaled down when a mode indication signal is enabled, so as to achieve a level dip event on a feedback signal, and accordingly driving the regulation unit enhancing its drivability of the output signal.

Abstract: A regulator comprises an amplifier, a bias circuit, and a current trimming circuit. The bias circuit is coupled to the amplifier and supplies a first bias current to the amplifier in a first mode of a system including the regulator. The current trimming circuit is coupled to the bias circuit to adjust the first bias current.

Abstract: A voltage regulator, alternatively operating in an active mode in response to an enabled mode indication signal, and operating in a standby mode in response to the disabled mode indication signal, is provided. The voltage regulator comprises a regulation unit and a feedback circuit. The regulation unit drives an output node with an output signal. The feedback circuit comprises a first resistance unit, connected between the output node and the feedback node, and a second resistance unit. The second resistance unit is connected between the feedback node and a ground reference voltage, and the resistance thereof is scaled down when a mode indication signal is enabled, so as to achieve a level dip event on a feedback signal, and accordingly driving the regulation unit enhancing its drivability of the output signal.

Abstract: An active bandpass filter is disclosed herein. The active bandpass filter has N transmission lines, N negative resistant circuits, a DC circuit, and at least (N?1) coupling circuit. Each transmission line has a first end and a second end. Each negative resistant circuit has a third end and a fourth end and is electrically coupled with a related transmission line, wherein the third end and the fourth end are electrically coupled with the first end and second end, respectively. The DC circuit provides a bias voltage for N negative resistant circuits, wherein the DC circuit electrically couples with N transmission lines via N coupling elements. Each coupling circuit has a fifth end and a sixth end and is electrically coupled with any two transmission lines, wherein the fifth end and sixth end are electrically coupled with the second end and the first end, respectively.