Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).

Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).

Abstract: Various embodiments are directed to a mechanism for reserving power resources to address non-uniform and complex routings on a redistribution layer of a flip-chip. Reserving power resources may be performed by rerouting RDL nets by, for example, identifying an initial RDL net route for a RDL net; defining an outer boundary relative to the initial RDL net route, wherein a perimeter of the outer boundary is defined at a defined distance away from the initial RDL net route; defining one or more blockages extending from bumps to intersect the outer boundary; subdividing the initial RDL net route into a plurality of net portions, wherein each net portion is bounded by a portion of the outer boundary and one or more of the blockages; and rerouting at least one of the plurality of net portions to be adjacent at least one blockage bounding the circuit net portion.

Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.

Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.

Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.

Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.