Patents by Inventor Hsien-Shih Chu
Hsien-Shih Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230261046Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.Type: ApplicationFiled: April 27, 2023Publication date: August 17, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Cheng Tung, Yun-Fan Chou, Te-Hao Huang, Hsien-Shih Chu, Feng-Ming Huang
-
Patent number: 11688764Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.Type: GrantFiled: September 2, 2021Date of Patent: June 27, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Cheng Tung, Yun-Fan Chou, Te-Hao Huang, Hsien-Shih Chu, Feng-Ming Huang
-
Patent number: 11678479Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.Type: GrantFiled: September 23, 2021Date of Patent: June 13, 2023Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Shi-Wei He, Te-Hao Huang, Hsien-Shih Chu, Yun-Fan Chou, Feng-Ming Huang
-
Publication number: 20220384191Abstract: A DRAM includes a substrate, a plurality of first active regions disposed on the substrate and arranged end-to-end along the first direction, and a plurality of second active regions disposed between the first active regions and arranged end-to-end along the first direction. The second active regions respectively have a first sidewall adjacent to a first trench between the second active region and one of the first active regions and a second sidewall adjacent to a second trench between the ends of the first active regions, wherein the second sidewall is taper than the first sidewall in a cross-sectional view.Type: ApplicationFiled: July 28, 2021Publication date: December 1, 2022Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yaoguang Xu, Hsien-Shih Chu, Yun-Fan Chou, Yu-Cheng Tung, Chaoxiong Wang
-
Publication number: 20220013528Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Shi-Wei HE, Te-Hao HUANG, Hsien-Shih CHU, Yun-Fan CHOU, Feng-Ming HUANG
-
Publication number: 20210399092Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.Type: ApplicationFiled: September 2, 2021Publication date: December 23, 2021Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Cheng TUNG, Yun-Fan CHOU, Te-Hao HUANG, Hsien-Shih CHU, Feng-Ming HUANG
-
Patent number: 11164877Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.Type: GrantFiled: December 11, 2019Date of Patent: November 2, 2021Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Shi-Wei He, Te-Hao Huang, Hsien-Shih Chu, Yun-Fan Chou, Feng-Ming Huang
-
Patent number: 11145715Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.Type: GrantFiled: December 11, 2019Date of Patent: October 12, 2021Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Cheng Tung, Yun-Fan Chou, Te-Hao Huang, Hsien-Shih Chu, Feng-Ming Huang
-
Publication number: 20210082923Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.Type: ApplicationFiled: December 11, 2019Publication date: March 18, 2021Inventors: Shi-Wei HE, Te-Hao HUANG, Hsien-Shih CHU, Yun-Fan CHOU, Feng-Ming HUANG
-
Publication number: 20210020742Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.Type: ApplicationFiled: December 11, 2019Publication date: January 21, 2021Inventors: Yu-Cheng TUNG, Yun-Fan CHOU, Te-Hao HUANG, Hsien-Shih CHU, Feng-Ming HUANG
-
Patent number: 10475649Abstract: A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.Type: GrantFiled: May 6, 2018Date of Patent: November 12, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Chen Chuang, Fu-Che Lee, Ming-Feng Kuo, Cheng-Yu Wang, Hsien-Shih Chu, Li-Chiang Chen
-
Publication number: 20190318929Abstract: A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.Type: ApplicationFiled: May 6, 2018Publication date: October 17, 2019Inventors: Yu-Chen Chuang, Fu-Che Lee, Ming-Feng Kuo, Cheng-Yu Wang, Hsien-Shih Chu, Li-Chiang Chen
-
Patent number: 10304679Abstract: A method of fabricating a mask includes providing a substrate. A first material layer is disposed on the substrate. Then, the first material layer is partly removed. A second trench is formed between the remaining first material layer. The second trench includes a height. Later, a second material layer is formed to conformally fill in the second trench. The second material layer includes a thickness. The thickness of the second material layer equals the height of the second trench. Finally, part of the second material layer is removed, and the remaining second material layer and the remaining first material layer comprise a second mask.Type: GrantFiled: January 22, 2018Date of Patent: May 28, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chieh-Te Chen, Hsien-Shih Chu, Cheng-Yu Wang
-
Patent number: 10249629Abstract: The present invention provides a method for forming buried word lines. Firstly, a substrate is provided, having a plurality of shallow trench isolations disposed therein, next, a plurality of first patterned material layers are formed on the substrate, a plurality of first recesses are disposed between every two adjacent first patterned material layers, a second patterned material layer is formed in the first recesses, and using the first patterned material layers and the second patterned material layer as the protect layers, and a first etching process is then performed, to form a plurality of second recesses in the substrate.Type: GrantFiled: January 22, 2018Date of Patent: April 2, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo, Chieh-Te Chen, Hsien-Shih Chu
-
Patent number: 10199258Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.Type: GrantFiled: December 20, 2016Date of Patent: February 5, 2019Assignees: United Microelectronics Corp., Fujian Jianhua Integrated Circuit Co., Ltd.Inventors: Chieh-Te Chen, Hsien-Shih Chu, Ming-Feng Kuo, Fu-Che Lee, Chien-Ting Ho, Chiung-Lin Hsu, Feng-Yi Chang, Yi-Wang Zhan, Li-Chiang Chen, Chien-Cheng Tsai, Chin-Hsin Chiu
-
Patent number: 10192777Abstract: A method of fabricating an STI trench includes providing a substrate. Later, a first mask is formed to cover the substrate. The first mask includes numerous sub-masks. A first trench is disposed between each sub-mask. Subsequently, a protective layer is formed to fill up the first trench. Then, a second mask is formed to cover the first mask. The second mask includes an opening. The sub-mask directly disposed under the opening is defined as a joint STI pattern. After that, the joint STI pattern is removed to transform the first mask into a third mask. Later, the second mask is removed followed by removing the protective layer. Finally, part of the substrate is removed by taking the third mask as a mask to form numerous STI trenches.Type: GrantFiled: December 27, 2017Date of Patent: January 29, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsien-Shih Chu, Ming-Feng Kuo, Yi-Wang Zhan, Li-Chiang Chen, Fu-Che Lee, Feng-Yi Chang
-
Patent number: 10062700Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.Type: GrantFiled: March 14, 2017Date of Patent: August 28, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang, Hsien-Shih Chu
-
Publication number: 20180226250Abstract: A method of fabricating a mask includes providing a substrate. A first material layer is disposed on the substrate. Then, the first material layer is partly removed. A second trench is formed between the remaining first material layer. The second trench includes a height. Later, a second material layer is formed to conformally fill in the second trench. The second material layer includes a thickness. The thickness of the second material layer equals the height of the second trench. Finally, part of the second material layer is removed, and the remaining second material layer and the remaining first material layer comprise a second mask.Type: ApplicationFiled: January 22, 2018Publication date: August 9, 2018Inventors: Chieh-Te Chen, Hsien-Shih Chu, Cheng-Yu Wang
-
Patent number: 10032631Abstract: A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between the mask. Subsequently, a mask material is formed to fill in the wider trench and the narrower trench. The top surface of the mask material overlapping the wider trench is lower than the top surface of the mask material overlapping the narrower trench. A photoresist layer is formed on the mask material overlapping the wider trench. Later, the mask material overlapping the narrower trench is etched while the mask material overlapping the wider trench is protected by the photoresist layer.Type: GrantFiled: May 10, 2017Date of Patent: July 24, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo, Hsien-Shih Chu, Cheng-Yu Wang, Yu-Chen Chuang
-
Publication number: 20180190663Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.Type: ApplicationFiled: March 14, 2017Publication date: July 5, 2018Inventors: Feng-Yi Chang, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang, Hsien-Shih Chu