Patents by Inventor Hsien-Ta Chung
Hsien-Ta Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10950712Abstract: A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.Type: GrantFiled: May 30, 2019Date of Patent: March 16, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chu-Ming Ma, Hung-Chi Huang, Hsien-Ta Chung
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Publication number: 20200350419Abstract: A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.Type: ApplicationFiled: May 30, 2019Publication date: November 5, 2020Inventors: Chu-Ming Ma, Hung-Chi Huang, Hsien-Ta Chung
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Patent number: 10290728Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first doped region, a second doped region, a first dielectric layer, a third doped region, a fourth doped region, a second dielectric layer and a conductive layer. The substrate has a first trench in a first area and a second trench in a second area. The first and second doped regions are disposed in the substrate respectively at two side of the first trench. The first dielectric layer is disposed on the sidewall of the first trench. The third doped region is disposed around the second trench. The fourth doped region is disposed in the third doped region at one side of the second trench. The second dielectric layer is disposed on the sidewall and bottom of the second trench. The conductive layer is disposed in the first and second trenches.Type: GrantFiled: April 14, 2017Date of Patent: May 14, 2019Assignee: United Microelectronics Corp.Inventors: Chu-Ming Ma, Chun-Yi Lin, Hung-Chi Huang, Hsien-Ta Chung
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Publication number: 20180261692Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first doped region, a second doped region, a first dielectric layer, a third doped region, a fourth doped region, a second dielectric layer and a conductive layer. The substrate has a first trench in a first area and a second trench in a second area. The first and second doped regions are disposed in the substrate respectively at two side of the first trench. The first dielectric layer is disposed on the sidewall of the first trench. The third doped region is disposed around the second trench. The fourth doped region is disposed in the third doped region at one side of the second trench. The second dielectric layer is disposed on the sidewall and bottom of the second trench. The conductive layer is disposed in the first and second trenches.Type: ApplicationFiled: April 14, 2017Publication date: September 13, 2018Applicant: United Microelectronics Corp.Inventors: Chu-Ming Ma, Chun-Yi Lin, Hung-Chi Huang, Hsien-Ta Chung
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Patent number: 9391177Abstract: The present invention provides a method for improving gate coupling ratio of a flash memory device and a protruding floating gate is formed. First, a substrate having a plurality of isolation structures is formed. Then, a first conductive layer is formed overlaying the substrate. A chemical-mechanical polishing process is performed to planarize the first conductive layer. After that, a portion of the isolation structures is removed, and a second conductive layer is formed overlaying the first conductive layer and the isolation structures. Finally, a lithography process with a photomask can be used to define a mask that covers the first conductive layer and the second conductive layer, and then an insulating layer is deposited overlaying the substrate, so that a third conductive layer is formed overlaying the insulating layer.Type: GrantFiled: August 13, 2015Date of Patent: July 12, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chu-Ming Ma, Chun-Yi Lin, Hung-Chi Huang, Hsien-Ta Chung
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Patent number: 6254676Abstract: A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.Type: GrantFiled: June 28, 1999Date of Patent: July 3, 2001Assignee: United Microelectronics Corp.Inventors: Gwo-Shii Yang, Michael W C Huang, Chien Chao Huang, Hsien-Ta Chung, Tri-Rung Yew
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Patent number: 6184142Abstract: A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.Type: GrantFiled: April 26, 1999Date of Patent: February 6, 2001Assignee: United Microelectronics Corp.Inventors: Hsien-Ta Chung, Chan-Lon Yang, Tong-Yu Chen, Tri-Rung Yew
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Patent number: 6159845Abstract: A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.Type: GrantFiled: September 11, 1999Date of Patent: December 12, 2000Assignees: United Microelectronics Corp., United Silicon IncorporatedInventors: Tri-Rung Yew, Water Lur, Hsien-Ta Chung
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Patent number: 6017817Abstract: A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.Type: GrantFiled: May 10, 1999Date of Patent: January 25, 2000Assignees: United Microelectronics Corp., United Semiconductor Corp.Inventors: Hsien-Ta Chung, Tri-Rung Yew, Water Lur