Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

Abstract: A semiconductor package includes a first die. The first die has a first side and a second side different from the first side and includes a first seal ring. The first seal ring includes a first portion at the first side and a second portion at the second side, and a width of the first portion is smaller than a width of the second portion.

Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.

Abstract: Semiconductor packages are provided. One of the semiconductor packages includes an integrated circuit, a die, an encapsulant and an inductor. The die is bonded to the integrated circuit. The encapsulant encapsulates the die over the integrated circuit. The inductor includes a plurality of first conductive patterns and a plurality of second conductive patterns. The first conductive patterns penetrate through the encapsulant. The second conductive patterns are disposed over opposite surfaces of the encapsulant. The first conductive patterns and the second conductive patterns are electrically connected to one another to form a spiral structure having two ends.

Abstract: A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

Abstract: A structure adapted to optical coupled to an optical fiber includes a photoelectric integrated circuit die, an electric integrated circuit die, a waveguide die and an insulating encapsulant. The electric integrated circuit die is over and electrically connected to the photoelectric integrated circuit die. The waveguide die is over and optically coupled to the photoelectric integrated circuit die, wherein the waveguide die includes a plurality of semiconductor pillar portions extending from the optical fiber to the photoelectric integrated circuit die. The insulating encapsulant laterally encapsulates the electric integrated circuit die and the waveguide die.

Abstract: A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.

Abstract: A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.

Abstract: The semiconductor structure includes a plurality of first dies, a plurality of second dies disposed over each of the first dies, and a dielectric material surrounding the plurality of first dies and the plurality of second die. Each of the second dies overlaps a portion of each first die.

Abstract: A disclosed semiconductor structure may include an interposer, a first semiconductor die electrically coupled to the interposer, a packaging substrate electrically coupled to the interposer, and a capping layer covering one or more of a first surface of the first semiconductor die and a second surface of the packaging substrate. The capping layer may be formed over respective surfaces of each of the first semiconductor die and the packaging substrate. In certain embodiments, the capping layer may be formed only on the first surface of the first semiconductor die and not formed over the package substrate. In further embodiments, the semiconductor structure may include a second semiconductor die, such that the capping layer covers a surface of only one of the first semiconductor die and the second semiconductor die. The semiconductor structure may include a molding compound die frame that is partially or completely covered by the capping layer.

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

Abstract: A semiconductor structure includes a substrate having a seal ring region and a circuit region, a dielectric interlayer over the substrate, one or more dielectric layers disposed over the dielectric interlayer, a connection structure disposed in the one or more dielectric layers in the seal ring region, and a metal plug disposed below the connection structure and disposed at least partially in the dielectric interlayer in the seal ring region. The connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers.

Abstract: A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

Abstract: A package is provided in accordance with some embodiments. The package includes a substrate including a first conductive via embedded in a first substrate core; a conductive pattern disposed on the first substrate core, wherein the conductive pattern includes a first conductive pad and a second conductive pad; a second substrate core disposed on the first substrate core and the conductive pattern; and a second conductive via disposed in the second substrate core and on the second conductive pad. The package also includes an encapsulant embedded in the second substrate core and in physical contact with the first conductive pad; a first die, including die connectors, embedded in the encapsulant and disposed on the first conductive pad; a redistribution structure disposed on the second conductive via, the die connectors and the encapsulant; and a second die disposed on the redistribution structure.

Abstract: An interposer for a semiconductor package and a method of fabricating an interposer including a peripheral metal pad surrounding an alignment mark. The alignment mark and the surrounding peripheral metal pad are formed on a first dielectric material layer of the interposer. A second dielectric material layer is located over the first dielectric material layer and at least partially over the peripheral metal pad structure and includes an recess extending around a periphery of the alignment mark. A third dielectric material layer is located over the second dielectric material layer and extends into the recess and contacts the alignment mark, the first dielectric material layer, and optionally a portion of the peripheral metal pad. The peripheral metal pad may enhance the adhesion between the first, second and third dielectric material layers near the alignment mark structure and thereby reduce the likelihood of crack formation.

Abstract: A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.

Abstract: A semiconductor structure includes an assembly including an interposer, at least one semiconductor die attached to the interposer including interposer bonding pads, and a die-side underfill material portion located between the interposer and the at least one semiconductor die, a packaging substrate including substrate bonding pads, an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads, a central underfill material portion laterally surrounding a first subset of the solder material portions, and at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion.

Abstract: A semiconductor structure includes: a first die, comprising a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first bonding dielectric layer over the first die; a first active bonding via in the first bonding dielectric layer, electrically connected to the first interconnect structure; and a plurality of first dummy bonding vias in the first bonding dielectric layer, wherein the first dummy bonding vias laterally surround the first active bonding via and are electrically floating.