Abstract: Arrays of static random access memory (SRAM) cells and methods of fabricating the same are provided. A first communication path is disposed a first distance from an edge of the array and is operable to control access to SRAM cells of a first row of the array for write operations. A second communication path is disposed a second distance from the edge of the array and is operable to control access to SRAM cells of a second row of the array for write operations. The second distance is different than the first distance. A first conductive structure is disposed a third distance from the edge of the array and is operable to control access to the SRAM cells of the first row for read operations. A second conductive structure is disposed the third distance from the edge of the array and is operable to control access to the SRAM cells of the second row for read operations.

Abstract: A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A method of providing a layout design of an SRAM cell includes: providing a substrate layout comprising a first oxide diffusion area, a second oxide diffusion area, a first polysilicon layout, and a second polysilicon layout, wherein the first polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area, and the second polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area; forming a first pull-up transistor on the first oxide diffusion area and the first polysilicon layout; forming a first pull-down transistor on the second oxide diffusion area and the first polysilicon layout; forming a second pull-up transistor on the first oxide diffusion area and the second polysilicon layout; and forming a second pull-down transistor on the second oxide diffusion area and second first polysilicon layout.

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled to the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled to the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: Arrays of static random access memory (SRAM) cells and methods of fabricating the same are provided. A first communication path is disposed a first distance from an edge of the array and is operable to control access to SRAM cells of a first row of the array for write operations. A second communication path is disposed a second distance from the edge of the array and is operable to control access to SRAM cells of a second row of the array for write operations. The second distance is different than the first distance. A first conductive structure is disposed a third distance from the edge of the array and is operable to control access to the SRAM cells of the first row for read operations. A second conductive structure is disposed the third distance from the edge of the array and is operable to control access to the SRAM cells of the second row for read operations.

Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.

Abstract: In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.

Abstract: A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract: In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract: A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a reading reference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating gate of the second reference cell are connected to an output of a logic circuit. The logic circuit receives at least one external state signal to determine whether the split-gate flash memory is ready to switch to reading mode or not, and then switches the first floating gate and the second floating gate between the state of activated and deactivated, so as to activate the first reference cell or the second reference cell to provide the reference current.