Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

Abstract: A system includes a mask. The system further includes a pellicle frame attached to the mask. The pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from a first side of the pellicle from to a second side of the pellicle frame. The pellicle frame further includes a flat bottom surface having only a single recess therein, wherein the flat bottom surface is free of an adhesive. The system further includes a gasket within the single recess.

Abstract: A pellicle for an extreme ultraviolet (EUV) photomask includes a pellicle frame and a main membrane attached to the pellicle frame. The main membrane includes a plurality of nanotubes, and each of the plurality of nanotubes is covered by a coating layer containing Si and one or more metal elements.

Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.

Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

Abstract: In a method of cleaning a photo mask, the photo mask is placed on a support such that a pattered surface faces down, and an adhesive sheet is applied to edges of a backside surface of the photo mask.

Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.

Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a solvent dipping treatment is performed to the nanotube layer by applying bubbles in a solvent to the nanotube layer.

Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.

Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.

Abstract: In a method of de-mounting a pellicle from a photo mask, the photo mask with the pellicle is placed on a pellicle holder. The pellicle is attached to the photo mask by a plurality of micro structures. The plurality of micro structures are detached from the photo mask by applying a force or energy to the plurality of micro structures before or without applying a pulling force to separate the pellicle from the photo mask. The pellicle is de-mounted from the photo mask. In one or more of the foregoing and following embodiments, the plurality of micro structures are made of an elastomer.

Abstract: A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a first absorber layer disposed on the capping layer, a first multilayer disposed over the first absorber layer, a second absorber layer disposed on the first multilayer layer, and a second multilayer, which is an uppermost layer of the reflective mask, disposed over the second absorber layer.

Abstract: A method includes performing a lithography process using a mask and a pellicle membrane; detaching the pellicle membrane from the mask after the lithography process is completed; performing an inspection process to the pellicle membrane, the inspection process including generating a laser beam toward the pellicle membrane from a laser source, such that the laser beam passes through the pellicle membrane; and generating an image by receiving the laser beam passing through the pellicle membrane using an image sensor; and determining whether a particle is present on the pellicle membrane or a pin hole is present in the pellicle membrane based on the image.

Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.

Abstract: A method includes forming a reflective multilayer over a substrate; depositing a first capping layer over the reflective multilayer, wherein the first capping layer is made of a ruthenium-containing material or a chromium-containing material; performing a treatment to the first capping layer to introduce nitrogen or fluorine into the first capping layer; forming an absorption layer over the first capping layer; and patterning the absorption layer.