Patents by Inventor Hsin-Chi Chen
Hsin-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817472Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.Type: GrantFiled: October 18, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
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Patent number: 11784198Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.Type: GrantFiled: June 2, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
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Publication number: 20230308755Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.Type: ApplicationFiled: June 1, 2023Publication date: September 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang
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Patent number: 11756913Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.Type: GrantFiled: June 15, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
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Patent number: 11735619Abstract: Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.Type: GrantFiled: June 6, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chiu-Jung Chen, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Volume Chien, Yun-Wei Cheng
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Patent number: 11706525Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.Type: GrantFiled: October 4, 2021Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang
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Publication number: 20230225099Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The first butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate structure.Type: ApplicationFiled: March 15, 2023Publication date: July 13, 2023Inventors: You Che CHUANG, Chih-Ming LEE, Hsin-Chi CHEN, Hsun-Ying HUANG
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Publication number: 20230118159Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer, and a color filter layer. The semiconductor substrate has a photosensitive region and an isolation region surrounding the photosensitive region. The radiation sensing member is embedded in the photosensitive region of the semiconductor substrate. The radiation sensing member has a material different from a material of the semiconductor substrate, and an interface between the radiation sensing member and the isolation region of the semiconductor substrate includes a direct band gap material. The device layer is under the semiconductor substrate and the radiation sensing member. The color filter layer is over the radiation sensing member and the semiconductor substrate.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
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Patent number: 11610901Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion in a second direction, different from the first direction, wherein the second portion directly contacts the first gate structure.Type: GrantFiled: December 3, 2020Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: You Che Chuang, Chih-Ming Lee, Hsin-Chi Chen, Hsun-Ying Huang
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Patent number: 11609559Abstract: A data processing system, including a cyclic correlation establishing module, a data pattern establishing module, and a data pattern alignment module, is provided. The cyclic correlation establishing module receives a plurality of first sensor data, obtained from a first sensor operation performed on processing devices, and receives a table of processing steps and cyclic procedures. The cyclic correlation establishing module obtains a data correlation of the first sensor data according to the number of sample points in a data cycle of the first sensor data and the table to correct the first sensor data. The data pattern establishing module obtains a plurality of first data pattern features from the first sensor data. The data pattern alignment module aligns a plurality of second sensor data obtained from a second sensor operation performed on the processing devices with the first sensor data according to the first data pattern features.Type: GrantFiled: May 14, 2020Date of Patent: March 21, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsin-Chi Chen, Chuang-Hua Chueh, Chun-Fang Chen, Chi-Heng Lin, Chun-Hsu Chen
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Patent number: 11532662Abstract: A method includes providing a semiconductor substrate having a front side surface and a back side surface opposite to the front side surface. A photosensitive region of the semiconductor substrate is etched to form a recess. A semiconductor material is deposited on the semiconductor substrate to form a radiation sensing member filling the recess. The semiconductor material has an optical band gap energy smaller than 1.77 eV. A device layer is formed over the front side surface of the semiconductor substrate and the radiation sensing member. A trench isolation is formed in an isolation region of the semiconductor substrate and extending from the back side surface of the semiconductor substrate.Type: GrantFiled: February 24, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
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Patent number: 11527563Abstract: A semiconductor structure includes a photodetector, which includes a substrate semiconductor layer having a doping of a first conductivity type, a second-conductivity-type photodiode layer that forms a p-n junction with the substrate semiconductor layer, a floating diffusion region that is laterally spaced from the second-conductivity-type photodiode layer, and a transfer gate electrode including a lower transfer gate electrode portion that is formed within the substrate semiconductor layer and located between the second-conductivity-type photodiode layer and the floating diffusion region. The transfer gate electrode may laterally surround the p-n junction, and may provide enhanced electron transmission efficiency from the p-n junction to the floating diffusion region. An array of photodetectors may be used to provide an image sensor.Type: GrantFiled: April 20, 2020Date of Patent: December 13, 2022Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Hsin-Chi Chen
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Publication number: 20220367546Abstract: A semiconductor structure includes a photodetector, which includes a substrate semiconductor layer having a doping of a first conductivity type, a second-conductivity-type photodiode layer that forms a p-n junction with the substrate semiconductor layer, a floating diffusion region that is laterally spaced from the second-conductivity-type photodiode layer, and a transfer gate electrode including a lower transfer gate electrode portion that is formed within the substrate semiconductor layer and located between the second-conductivity-type photodiode layer and the floating diffusion region. The transfer gate electrode may laterally surround the p-n junction, and may provide enhanced electron transmission efficiency from the p-n junction to the floating diffusion region. An array of photodetectors may be used to provide an image sensor.Type: ApplicationFiled: July 19, 2022Publication date: November 17, 2022Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Hsin-Chi Chen
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Publication number: 20220367391Abstract: A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu WEI, Cheng-Yuan LI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
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Publication number: 20220359751Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh SINGH, Hsin-Chi CHEN, Kun-Tsang CHUANG
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Patent number: 11495632Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of isolation structures are each disposed between two respective radiation-sensing regions. The isolation structures protrude out of the second side of the substrate.Type: GrantFiled: August 31, 2020Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Lee, Yun-Wei Cheng, Yung-Lung Hsu, Hsin-Chi Chen
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Publication number: 20220352307Abstract: A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gulbagh Singh, Kun-Tsang Chuang, Hsin-Chi Chen
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Patent number: 11482506Abstract: A front-side peripheral region of a first wafer may be edge-trimmed by performing a first pre-bonding edge-trimming process. A second wafer to be bonded with the first wafer is provided. Optionally, a front-side peripheral region of the second wafer may be edge-trimmed by performing a second pre-bonding edge-trimming process. A front surface of the first wafer is bonded to a front surface of a second wafer to form a bonded assembly. A backside of the first wafer is thinned by performing at least one wafer thinning process. The first wafer and a front-side peripheral region of the second wafer may be edge-trimmed by performing a post-bonding edge-trimming process. The bonded assembly may be subsequently diced into bonded semiconductor chips.Type: GrantFiled: March 31, 2020Date of Patent: October 25, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Feng-Chien Hsieh, Hsin-Chi Chen, Kuo-Cheng Lee, Mu-Han Cheng, Yun-Wei Cheng
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Publication number: 20220336411Abstract: A front-side peripheral region of a first wafer may be edge-trimmed by performing a first pre-bonding edge-trimming process. A second wafer to be bonded with the first wafer is provided. Optionally, a front-side peripheral region of the second wafer may be edge-trimmed by performing a second pre-bonding edge-trimming process. A front surface of the first wafer is bonded to a front surface of a second wafer to form a bonded assembly. A backside of the first wafer is thinned by performing at least one wafer thinning process. The first wafer and a front-side peripheral region of the second wafer may be edge-trimmed by performing a post-bonding edge-trimming process. The bonded assembly may be subsequently diced into bonded semiconductor chips.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Mu-Han Cheng, Kuo-Cheng Lee, Hsin-Chi Chen
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Patent number: 11462642Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.Type: GrantFiled: September 24, 2020Date of Patent: October 4, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang