Abstract: A method of making a trench capacitor including the following steps: forming a first trench of predetermined depth into a semiconductor substrate; forming an electrode plate on the side-wall of a bottom of the first trench; forming a dielectric layer on the electrode plate; forming a first conductive portion on the dielectric layer, wherein the first conductive portion fills the bottom of the first trench to form a second trench; forming an insulation layer to fill the bottom portion of the second trench to make a third trench in the second trench; forming a conductive spacer along the side-wall of the third trench; etching the insulation layer using the conductive spacer as a mask to form a forth trench; and then filling the forth trench with a conductive material.

Abstract: A method of fabricating a stack crown capacitor of a dynamic random access memory (DRAM) cell by using an oxynitride mask is disclosed. First, a dielectric layer and a silicon nitride layer are sequentially deposited over a substrate with an electrical device. Next, forming a contact in the silicon nitride layer and the dielectric layer, and depositing a first polysilicon layer to fill the contact. Next, depositing an oxide layer and an oxynitride layer sequentially, and then defining a bottom electrode pattern for etching the oxynitride layer and the oxide layer. Then, laterally etching the oxide layer, and depositing a second polysilicon layer. Next, etching the second polysilicon layer and the first polysilicon layer by using the oxynitride layer as a mask to form the bottom electrode. Next, removing the oxynitride layer, the oxide layer and partial silicon nitride layer. Finally, forming an interelectrode dielectric layer and a top electrode.

Abstract: A method of rounding the bottom electrode top surface of a stack crown capacitor by using chemical oxidation is disclosed. First, forming a bottom electrode of a stack crown capacitor on a semiconductor substrate. Next, oxidizing the bottom electrode top surface by using oxidant dipping. Finally, removing the oxide from the bottom electrode top surface to achieve the goal of surface planarization. Thereafter, repeating the above steps to meet the requirement of surface planarization.

Abstract: A underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition is disclosed. First, a layer of metal pattern is defined on a semiconductor substrate, then a layer of dielectric underlayer is deposited, next, a high O.sub.3 /TEOS interlayer dielectric is formed to achieve planarization. The key point of this process is to apply materials with higher refraction index than conventional PE-TEOS for forming interlayer dielectric underlayer. The mentioned material can be PE-SiH.sub.4 with a constant or decreasing refraction index with the distance from the semiconductor substrate. The underlayer can also be bi-layer structure consisting of high refraction index bottom layer and low refraction index surface layer. This invention can effectively suppress the problem caused from high surface sensitivity of O.sub.3 /TEOS, and improve the quality of interlayer dielectric planarization process dramatically.