Patents by Inventor Hsin-Chun Chang
Hsin-Chun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955441Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.Type: GrantFiled: March 28, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
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Publication number: 20230402384Abstract: Material properties of graphene can be leveraged to improve performance of interconnects in an integrated circuit. One way to circumvent challenges involved in depositing graphene onto a copper surface is to incorporate graphene into the bulk metal layer to create a hybrid metal/graphene interconnect structure. Such a hybrid structure can be created instead of, or in addition to, forming a graphene film on the metal surface as a metal capping layer. A first method for embedding graphene into a copper damascene layer is to alternate the metal fill process with graphene deposition to create a composite graphene matrix. A second method is to implant carbon atoms into a surface layer of metal. A third method is to disperse graphene flakes in a damascene copper plating solution to create a distributed graphene matrix. Any combination of these methods can be used to enhance conductivity of the interconnect.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong LIN, Yinlung LU, Jun HE, Hsuan-Ming HUANG, Hsin-Chun CHANG
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Publication number: 20230386973Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Ming-Hong HSIEH, Ming-Yih WANG, Yinlung LU
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Patent number: 11616002Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: GrantFiled: January 29, 2021Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu
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Publication number: 20220367323Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu
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Publication number: 20220216165Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong LIN, Kuo-Yen LIU, Hsin-Chun CHANG, Tzu-Li LEE, Yu-Ching LEE, Yih-Ching WANG
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Patent number: 11302654Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.Type: GrantFiled: September 11, 2020Date of Patent: April 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
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Publication number: 20210375723Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: January 29, 2021Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Ming-Hong HSIEH, Ming-Yih WANG, Yinlung LU
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Publication number: 20200411452Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong LIN, Kuo-Yen LIU, Hsin-Chun CHANG, Tzu-Li LEE, Yu-Ching LEE, Yih-Ching WANG
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Patent number: 10777510Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.Type: GrantFiled: January 3, 2017Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
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Patent number: 10431541Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.Type: GrantFiled: March 20, 2017Date of Patent: October 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Hui Lee, Yung-Sheng Huang, Yung-Huei Lee
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Publication number: 20180269148Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.Type: ApplicationFiled: March 20, 2017Publication date: September 20, 2018Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Hui LEE, Yung-Sheng HUANG, Yung-Huei LEE
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Publication number: 20180151511Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.Type: ApplicationFiled: January 3, 2017Publication date: May 31, 2018Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
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Patent number: 9941159Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.Type: GrantFiled: September 2, 2016Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee
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Publication number: 20160372368Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE
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Patent number: 9449919Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.Type: GrantFiled: February 12, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee
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Publication number: 20160240472Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.Type: ApplicationFiled: February 12, 2015Publication date: August 18, 2016Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE
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Patent number: 6059161Abstract: A trigger assembly for a power stapler includes a U-shaped trigger member pivotally connected to the power stapler and having two inclined and elongated slots in the two plates thereof. A pressing member has a flange extending from one of two surfaces thereof and an aperture is defined through the pressing member. The pressing member has two lugs so that the pressing member is pivotally between the two plates of the trigger member. A pin movably extends through the slots in the trigger member and the two lugs. The pressing member is slightly lifted within the slots when the piston rod of the power stapler inserted into the aperture for the single shoot so that the pressing member is not returned to its original position except the safety member is removed from the pressing member.Type: GrantFiled: August 19, 1999Date of Patent: May 9, 2000Assignee: Nailermate Enterprise CorporationInventors: Hsin-Chun Chang, Arosun Lee