Patents by Inventor Hsin-Han Chen
Hsin-Han Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240168324Abstract: A decoration panel includes a first substrate, a first transparent conductive element, a transparent structure, a second substrate, a second transparent conductive element, and a first cholesteric liquid crystal layer. The first transparent conductive element is disposed on the first substrate. The transparent structure is disposed on the first substrate. The second substrate is disposed opposite to the first substrate. The second transparent conductive element is disposed on the second substrate. The first cholesteric liquid crystal layer is disposed between the first transparent conductive element and the second transparent conductive element. A display apparatus is adapted to render a decoration pattern, and the decoration pattern corresponds to the transparent structure. Moreover, a display apparatus including the decoration panel is also provided.Type: ApplicationFiled: November 20, 2023Publication date: May 23, 2024Applicant: AUO CorporationInventors: Chien-Chuan Chen, Wei-Jen Su, Hsin Chiang Chiang, Chun-Han Lee, Peng-Yu Chen, Ko-Ruey Jen, Yung-Chih Chen
-
Publication number: 20240170299Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Inventors: KUN-JU LI, ANG CHAN, HSIN-JUNG LIU, WEI-XIN GAO, JHIH-YUAN CHEN, CHUN-HAN CHEN, ZONG-SIAN WU, CHAU-CHUNG HOU, I-MING LAI, FU-SHOU TSAI
-
Patent number: 11991479Abstract: The disclosure provides a time-lapse photographic device. The time-lapse photographic device includes a camera module, a drive module, an environment detection module, and a control unit. The drive module is connected to the camera module to drive the camera module to rotate. The environment detection module is configured to detect an external environment of the time-lapse photographic device to generate an environment detection signal. The control unit is electrically connected to the camera module, the drive module, and the environment detection module. The control unit generates, according to a shooting stop parameter, a plurality of intermittent drive signals to control the drive module, and controls the camera module to shoot at intervals of the drive signals. The control unit adjusts operation of at least one of the camera module and the drive module according to the environment detection signal.Type: GrantFiled: February 15, 2022Date of Patent: May 21, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Hsin-Yi Pu, Kai-Yu Hsu, Lai-Peng Wong, Chieh Li, Ting-Han Chang, Ching-Xsuan Chen
-
Publication number: 20240154642Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
-
Publication number: 20240134239Abstract: A display device including a substrate, a cholesteric liquid crystal layer, and a transparent electrode layer that are sequentially stacked is provided. The cholesteric liquid crystal layer includes cholesteric liquid crystal molecules and a plurality of transparent photoresist structures. Each of the transparent photoresist structures is a closed structure, and the cholesteric liquid crystal molecules are respectively accommodated in a plurality of patterned areas respectively surrounded by the transparent photoresist structures, so as to form a plurality of cholesteric liquid crystal patterns. The transparent electrode layer includes a plurality of sub-electrodes. The cholesteric liquid crystal patterns are respectively driven by the sub-electrodes. An orthogonal projection of each of the transparent photoresist structures on the substrate falls in an orthogonal projection of a corresponding sub-electrode of the sub-electrodes on the substrate.Type: ApplicationFiled: October 22, 2023Publication date: April 25, 2024Applicant: AUO CorporationInventors: Chun-Han Lee, Chien-Chuan Chen, Ju-Wen Chang, Hsin Chiang Chiang, Peng-Yu Chen
-
Publication number: 20240118526Abstract: An imaging system lens assembly includes a first lens group and a second lens group. The first lens group includes a first catadioptric lens element and a second catadioptric lens element, the second lens group includes at least one lens element. Each of an object-side surface and an image-side surface of the first catadioptric lens element and the second catadioptric lens element includes a central region and a peripheral region. The peripheral region of the object-side surface of the first catadioptric lens element includes a first refracting surface. The peripheral region of the image-side surface of the second catadioptric lens element includes a first reflecting surface. The central region of the object-side surface of the first catadioptric lens element includes a second reflecting surface. The central region of the image-side surface of the second catadioptric lens element includes a last refracting surface.Type: ApplicationFiled: September 26, 2023Publication date: April 11, 2024Inventors: Shih-Han CHEN, Cheng-Yu TSAI, Hsin-Hsuan HUANG
-
Patent number: 11944486Abstract: An analysis method and an electronic apparatus for breast image are provided. The method includes the following steps. One or more breast ultrasound images are obtained. The breast ultrasound images are used for forming a three-dimensional (3D) breast model. A volume of interest (VOI) in the breast ultrasound image is obtained by applying a detection model on the 3D breast model. The VOI is compared with a tissue segmentation result. The VOI is determined as a false positive according to a compared result between the VOI and the tissue segmentation result. The compared result includes that the VOI is located at a glandular tissue based on the tissue segmentation result. In response to the VOI being located in the glandular tissue of the tissue segmentation result, the VOI is compared with the lactiferous duct in the 3D breast model.Type: GrantFiled: July 19, 2021Date of Patent: April 2, 2024Assignee: TAIHAO MEDICAL INC.Inventors: Jen-Feng Hsu, Hong-Hao Chen, Rong-Tai Chen, Hsin-Hung Lai, Wei-Han Teng
-
Patent number: 11923205Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
-
Publication number: 20210381885Abstract: The disclosure provides a light-emitting element inspection device optically connected to at least one light-emitting element of a test object and including a dark box, a slide rail, an image-capturing device, a light-entrance plate, and a processor. The slide rail and the image-capturing device are disposed in the dark box. The image-capturing device slides on the slide rail. The light-entrance plate is disposed on one side of the dark box and has at least one hole optically connected to the light-emitting element. The image-capturing device is aligned with the light-entrance plate to capture an image of the light-entrance plate. The processor is coupled to the image-capturing device and is adapted to obtain a set of RGB values of the image, convert the RGB values into a set of HSV values, and determine whether the light-emitting element of the test object conforms to a standard based on the HSV values.Type: ApplicationFiled: March 26, 2021Publication date: December 9, 2021Applicant: PEGATRON CORPORATIONInventors: Shao-Han Chiang, Tzu-Hsiang Kao, Tsung-Wei Tseng, Wen-Shau Peng, Jyun-Yi Wu, Hsin-Han Chen, Ting-Yi Wu, Hsiao-Jung Ou, Wei-Fu Chen, Chih-Yuan Lin, Li-Chia Wang
-
Publication number: 20210323012Abstract: A liquid dispenser is mountable to a container having an interior portion. The liquid dispenser includes a pump and a pressurization tube that includes a first end connected to the pump, a second end in fluid communication with the container interior, and a pressure release aperture. The dispenser further includes a valve that is located in the housing and includes a first port in fluid communication with an outside area, a second port in fluid communication with the pressure relief aperture, and a third port in fluid communication with the interior cavity of the housing. The valve further includes a plug selectively movable between a first position, in which the plug blocks the third port, and a second position, in which the plug blocks the second port.Type: ApplicationFiled: July 24, 2020Publication date: October 21, 2021Inventors: Yeh-Yi Chung, Hsin-Han Chen
-
Patent number: 8995100Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.Type: GrantFiled: March 26, 2012Date of Patent: March 31, 2015Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen
-
Publication number: 20140192070Abstract: The present invention discloses a configure image process system and a configure image process method thereof applicable to a predetermine image process structure. The configure image process system includes N pieces of logic hardware and a control module, wherein N is a positive integer. Each piece of the logic hardware respectively corresponds to an algorithm structure, and the control module connects to each piece of the logic hardware. The control module can selectively apply the N pieces of logic hardware to combine at least one part of the predetermine image process structure to perform the image process.Type: ApplicationFiled: January 31, 2013Publication date: July 10, 2014Applicant: ALTEK CORPORATIONInventors: KUEI-HUNG CHENG, HSIN-HAN CHEN, YEN-PING TENG
-
Publication number: 20130249046Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.Type: ApplicationFiled: March 26, 2012Publication date: September 26, 2013Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen