Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.

Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad. The daughterboard includes at least one second signal pad electronically connected to the at least one first signal pad for electronically connecting the daughterboard to the motherboard.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: A method for controlling impedance of a multi-layer PCB includes establishing a geometric model using simulation software according to a structure of the multi-layer PCB. A first variable (S) and a second variable (W) are respectively defined in the simulation software. The variable S is set equal to a first desired value. An impedance (R) of the transmission line is set equal to a second desired value. The variable W is set to a value according to a relationship between R, S, and W.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite to the first membrane surface, located in a pushed area of the membrane, and electrically connected to the circuit layer through the conductive through-vias. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. The bumps are electrically connected to the conductive layer through the conductive through-vias.

Abstract: A testing assembly for an electrical test of an electronic package is provided. The testing assembly includes a testing circuit board and a testing socket mounted thereon. The testing socket includes an insulating body and a plurality of pins. The insulating body has a holding surface for supporting a contact surface of the electronic package, and at least one low-dielectric constant region located between two neighboring pins, and the dielectric constant of the low-electric constant region is lower than other regions of the insulating body. In addition, the pins passing through the insulating body are configured as the electric channels between a plurality of contacts on the contact surface and a plurality of testing pads on a conductive layer on a surface of the testing circuit board. Furthermore, the pins include a signal pin, and one end of the signal pin is electrically coupled to the signal testing pad.

Abstract: A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite to the first membrane surface, located in a pushed area of the membrane, and electrically connected to the circuit layer through the conductive through-vias. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. The bumps are electrically connected to the conductive layer through the conductive through-vias.

Abstract: A testing assembly for an electrical test of an electronic package is provided. The testing assembly includes a testing circuit board and a testing socket mounted thereon. The testing socket includes an insulating body and a plurality of pins. The insulating body has a holding surface for supporting a contact surface of the electronic package, and at least one low-dielectric constant region located between two neighboring pins, and the dielectric constant of the low-electric constant region is lower than other regions of the insulating body. In addition, the pins passing through the insulating body are configured as the electric channels between a plurality of contacts on the contact surface and a plurality of testing pads on a conductive layer on a surface of the testing circuit board. Furthermore, the pins include a signal pin, and one end of the signal pin is electrically coupled to the signal testing pad.