Abstract: An ESD circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first ESD current path, a second ESD current path, a biasing circuit and a control circuit. The control circuit is connected between the pad and a first node. The first P-type transistor is connected with the pad, the control circuit and a second node. The first ESD current path is connected between the second node and the first node. The second ESD current path is connected between the second node and the first node. The second P-type transistor is connected with the pad, the control circuit and a third node. The biasing circuit is connected between the third node and the first node. The third P-type transistor is connected with the pad, the third node, and a fourth node. The internal circuit is connected between the fourth node and the first node.

Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.

Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.

Abstract: An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.

Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.

Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.

Abstract: An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.

Abstract: An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.

Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.

Abstract: An ESD circuit is connected with a pad. The ESD circuit includes a voltage divider, a RC circuit and a path control circuit. The voltage divider is connected between the pad and a first node and provides plural divided voltages. The RC circuit is connected between the pad and the first node. The RC circuit receives the plural divided voltages and provides a control circuit. The path control circuit is connected with the pad and the first node. The path control circuit receives the plural divided voltages and the control voltage. When the pad receives a first ESD zap, the RC circuit controls the path control circuit to turn on a first ESD current path. Consequently, an ESD current flows from the pad to the first node through the first ESD current path.

Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.

Abstract: An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD release transistor, at least one stress release transistor, a control circuit, and a voltage division circuit. The ESD release transistor is coupled to a reference voltage terminal of a circuit to be protected. The at least one stress release transistor is coupled between a voltage input terminal of the circuit to be protected and the ESD release transistor. The control circuit turns off the ESD release transistor during a normal operation, and turns on the ESD release transistor during a positive ESD zapping. The voltage division circuit provides at least one divisional voltage for turning on the at least one stress release transistor during the normal operation and the positive ESD zapping.

Abstract: An ESD circuit is connected with a pad. The ESD circuit includes a voltage divider, a RC circuit and a path control circuit. The voltage divider is connected between the pad and a first node and provides plural divided voltages. The RC circuit is connected between the pad and the first node. The RC circuit receives the plural divided voltages and provides a control circuit. The path control circuit is connected with the pad and the first node. The path control circuit receives the plural divided voltages and the control voltage. When the pad receives a first ESD zap, the RC circuit controls the path control circuit to turn on a first ESD current path. Consequently, an ESD current flows from the pad to the first node through the first ESD current path.

Abstract: An ESD circuit is connected with a pad. The ESD circuit includes a P-type transistor, an N-type transistor and a control circuit. A first source/drain terminal of the P-type transistor is connected with the pad. A first source/drain terminal of the N-type transistor is connected with a second source/drain terminal of the P-type transistor. A second source/drain terminal of the N-type transistor is connected with a first node. The control circuit is connected with the pad, the first node, a gate terminal of the P-type transistor and a gate terminal of the N-type transistor. When the pad receives an ESD zap, the control circuit provides a first voltage drop to the P-type transistor and provides a second voltage drop to the N-type transistor, so that the P-type transistor and the N-type transistor are turned on.

Abstract: In the present invention a signal generator is described for use in measuring the effects of wire to wire coupling in integrated circuits. A signal is connected to a wire that is surrounded by reference wires. A set of latches are used to set up and initiate signals simultaneously on the reference wires and the signal wire. Using latch reset and preset in phase and out of phase signals are created on the reference and signal wires that are routed in parallel. Several stages can be concatenated together in series to produce a delay resulting from coupling that can be easily measure. The latches at the beginning of each stage are activated by an enable signal to keep the signals in the reference wires and the signal wire synchronized.

Abstract: In the present invention A signal generator is described for use in measuring the effects of wire to wire coupling in integrated circuits. A signal is connected to a wire that is surrounded by reference wires. A set of latches are used to set up and initiate signals simultaneously on the reference wires and the signal wire. Using latch reset and preset in phase and out of phase signals are created on the reference and signal wires that are routed in parallel. Several stages can be concatenated together in series to produce a delay resulting from coupling that can be easily measure. The latches at the beginning of each stage are activated by an enable signal to keep the signals in the reference wires and the signal wire synchronized.