Patents by Inventor HSIN-LUN TSENG

HSIN-LUN TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154642
    Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
  • Publication number: 20230341765
    Abstract: A method includes: providing a first design layout including a plurality of cells; updating a first cell of the plurality of cells using optical proximity correction to provide a first updated cell and a data set; and updating a second cell from remaining cells in the first design layout based on the data set and a model without involvement of optical proximity correction to provide a second updated cell, wherein the model includes hidden layers including nodes and is trained to obtaining converged values of the nodes of the hidden layers through providing a mapping of edge segments before lithography enhancement and edge segments after lithography enhancement using optical proximity correction, and wherein at least one of the providing, and updating is executed by one or more processors.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI
  • Patent number: 11726402
    Abstract: A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Lin Chu, Hsin-Lun Tseng, Sheng-Wen Huang, Chih-Chung Huang, Chi-Ming Tsai
  • Publication number: 20210349389
    Abstract: A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI
  • Patent number: 11079672
    Abstract: A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Lin Chu, Hsin-Lun Tseng, Sheng-Wen Huang, Chih-Chung Huang, Chi-Ming Tsai
  • Publication number: 20200133117
    Abstract: A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.
    Type: Application
    Filed: August 12, 2019
    Publication date: April 30, 2020
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI