Patents by Inventor Hsin-Pang Lu
Hsin-Pang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11294577Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.Type: GrantFiled: March 26, 2020Date of Patent: April 5, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsiao-Hua Lu, Hsin-Pang Lu
-
Publication number: 20210263656Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.Type: ApplicationFiled: March 26, 2020Publication date: August 26, 2021Inventors: Hsiao-Hua Lu, Hsin-Pang Lu
-
Patent number: 10580499Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.Type: GrantFiled: September 21, 2017Date of Patent: March 3, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
-
Patent number: 10352986Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.Type: GrantFiled: May 25, 2016Date of Patent: July 16, 2019Assignee: United Microelectronics Corp.Inventors: Hsin-Pang Lu, Hsin-Wen Chen
-
Publication number: 20190043587Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.Type: ApplicationFiled: September 21, 2017Publication date: February 7, 2019Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
-
Publication number: 20170345720Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.Type: ApplicationFiled: May 25, 2016Publication date: November 30, 2017Inventors: Hsin-Pang Lu, Hsin-Wen Chen
-
Patent number: 9263134Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.Type: GrantFiled: March 17, 2014Date of Patent: February 16, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Nan Mou, Hsin-Pang Lu, Hsi-Wen Chen
-
Publication number: 20150262621Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Nan Mou, Hsin-Pang Lu, Hsi-Wen Chen
-
Patent number: 9093131Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.Type: GrantFiled: December 17, 2013Date of Patent: July 28, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsi-Wen Chen, Hsin-Pang Lu
-
Publication number: 20150170718Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsi-Wen Chen, Hsin-Pang Lu
-
Publication number: 20150095728Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.Type: ApplicationFiled: September 30, 2013Publication date: April 2, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Pang Lu, Hsi-Wen Chen, Ya-Nan Mou, Chung-Cheng Tsai, Hsiao-Chieh Sung, Yin-Ju Hsiao
-
Publication number: 20140376316Abstract: A programmable memory cell includes a non-volatile memory unit, a reference current generator and a readout unit. The non-volatile memory unit is configured to be performed by a program operation, a read operation or an erase operation. The reference current generator is configured to generate a reference current; wherein a value of the reference current is dynamically modulated according to a count number of the program and erase operations performed on the non-volatile memory unit. The readout unit, electrically coupled to the non-volatile memory unit and the reference current generator, is configured to read a data stored in the non-volatile memory cell according to the reference current. A data read method applied to the aforementioned programmable memory cell is also provided.Type: ApplicationFiled: June 23, 2013Publication date: December 25, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Shi-Wen CHEN, Hsin-Pang Lu
-
Patent number: 8804440Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: GrantFiled: March 26, 2014Date of Patent: August 12, 2014Assignee: United Microelectronics CorporationInventors: Shi-Wen Chen, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou
-
Publication number: 20140211573Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: ApplicationFiled: March 26, 2014Publication date: July 31, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Shi-Wen CHEN, Hsin-Pang LU, Chung-Cheng TSAI, Ya-Nan MOU
-
Publication number: 20140204686Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: ApplicationFiled: March 26, 2014Publication date: July 24, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Shi-Wen CHEN, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou
-
Patent number: 8767485Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: GrantFiled: March 26, 2014Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Shi-Wen Chen, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou
-
Patent number: 8724404Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: GrantFiled: October 15, 2012Date of Patent: May 13, 2014Assignee: United Microelectronics Corp.Inventors: Shi-Wen Chen, Hsin-Pang Lu, Chung-Cheng Tsai, Ya-Nan Mou
-
Publication number: 20140104962Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-Wen CHEN, Hsin-Pang LU, Chung-Cheng TSAI, Ya-Nan MOU
-
Publication number: 20100026380Abstract: A reference generating apparatus and a sampling apparatus thereof are provided. The coding module is configured to code and decode a first reference signal to retrieve a second reference signal with less power than generating the first reference signal. The second reference signal is identical to the first reference signal in amplitude.Type: ApplicationFiled: July 30, 2008Publication date: February 4, 2010Applicant: MEMOCOM CORP.Inventors: Isaac Y. Chen, Jin-Lung Kuo, Hsin Pang Lu
-
Patent number: 6967875Abstract: The memory system includes a plurality of memory cells that are arranged for forming a column, and the plurality of memory cells are coupled with a first bitline and a second bitline individually. Additionally, the memory system further includes a bitline conditioning circuit to perform the pre-charge procedure thereof; and that includes a plurality of wordlines. Furthermore, the memory system further includes a compensating-circuit to keep the voltage that is requirement for the access procedure, wherein the bitline conditioning circuit and the compensating-circuit couple to receive a pair of complemental signals so as to control the interaction between the pre-charge procedure and the compensation procedure from each other.Type: GrantFiled: April 21, 2003Date of Patent: November 22, 2005Assignee: United Microelectronics Corp.Inventors: Chung-Hao Chen, Hsin-Pang Lu