Abstract: A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.

Abstract: The present invention discloses a system in package (SIP) integrated circuit and a packaging method thereof. The SIP integrated circuit includes one or more first block dices produced by a first process and one or more second block dices produced by a second process. The first block dices are electrically connected to the second block dices. The first block dices and the second block dices are packaged into a system.

Abstract: A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.

Abstract: The present invention discloses a structured ASIC layout architecture, which includes a fixed body region and a programmable layout region. The fixed body region includes a tunnel wire or multiple tunnel wires for providing a function capability or multiple function capability. The programmable layout region is disposed on the fixed body region and is connected to the fixed body region, wherein the programmable layout region utilizes the tunnel wires of the fixed body region to propagate electrical signals.

Abstract: The present invention discloses a system in package (SIP) integrated circuit and a packaging method thereof. The SIP integrated circuit includes one or more first block dices produced by a first process and one or more second block dices produced by a second process. The first block dices are electrically connected to the second block dices. The first block dices and the second block dices are packaged into a system.

Abstract: A flip-flop having improved set-up time and a method used with are provided. The flip-flop comprises a first master latch, a first selector, a second master latch, a second selector, and a slave latch. The first master latch receives the critical data and is used to latch the critical data. The first selector receives a plurality of non-critical data and outputs a first selected data to the second latch. The second master latch is used to latch the first selected data. The second selector is coupled to the first master latch and the second master latch in order to output a second selected data to the slaver latch. The slave latch is used to latch and output the second selected data.

Abstract: An input and output circuit of an integrated circuit chip for exchanging signals between logic circuits of the integrated circuit chip and a system. The input and output circuit includes a plurality of power rings for providing a plurality of power sources, a plurality of input and output pads for transmitting signals, a sequence of input and output cells for transmitting signals, and a plurality of electrostatic discharge protection cells deposited within the sequence of input and output cells for performing electrostatic discharge protection for the input and output cells, wherein the plurality of electrostatic discharge protection cells are not coupled to any input and output pads.

Abstract: A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality of vias within a via layer disposed between the first and second routing layers for connecting the metal traces on the first and second routing layers according to a first current route defined by a predetermined circuit layout design to connect a first node and a second node so as to establish a second current route equivalent to the first current route.

Abstract: A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program the basic units for building a clocked logic circuit and a non-clocked logic circuit without placing restrictions on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body.

Abstract: An input and output circuit of an integrated circuit chip for exchanging signals between logic circuits of the integrated circuit chip and a system. The input and output circuit includes a plurality of power rings for providing a plurality of power sources, a plurality of input and output pads for transmitting signals, a sequence of input and output cells for transmitting signals, and a plurality of electrostatic discharge protection cells deposited within the sequence of input and output cells for performing electrostatic discharge protection for the input and output cells, wherein the plurality of electrostatic discharge protection cells are not coupled to any input and output pads.

Abstract: A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program the basic units for building a clocked logic circuit and a non-clocked logic circuit without placing restrictions on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body.

Abstract: A method for forming a metal programmable integrated circuit that can use a plurality of clock sources and balance clock skew. The integrated circuit has a semiconductor body. The method includes step (a) used for forming a plurality of basic units on the semiconductor body wherein each basic unit has at least a logic module, at least a driving module, and at least a storage module, and step (b) used for forming a metal layer for programming the logic module to be able to perform logic operations, programming the driving module to able to drive an input signal inputted into the driving module, and programming the storage module to be able to store data after performing step (a).

Abstract: A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality of vias within a via layer disposed between the first and second routing layers for connecting the metal traces on the first and second routing layers according to a first current route defined by a predetermined circuit layout design to connect a first node and a second node so as to establish a second current route equivalent to the first current route.

Abstract: A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM), cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.

Abstract: A method for forming a metal programmable integrated circuit that can use a plurality of clock sources and balance clock skew. The integrated circuit has a semiconductor body. The method includes step (a) used for forming a plurality of basic units on the semiconductor body wherein each basic unit has at least a logic module, at least a driving module, and at least a storage module, and step (b) used for forming a metal layer for programming the logic module to be able to perform logic operations, programming the driving module to able to drive an input signal inputted into the driving module, and programming the storage module to be able to store data after performing step (a).

Abstract: A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM) cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.