Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.

Abstract: A display panel with reduced short-wavelength blue light is provided and includes a backlight module and an LCD panel. The backlight module includes a plurality of LEDs, each of which includes a blue LED die configured to emit blue light with a peak wavelength ranging from 455 to 475 nm. The present invention may efficiently reduce blue light with wavelengths less than 455 nm to protect eyes, and may not reduce display brightness and encounter color aberration. Moreover, the backlight module may further include an optical filter sheet or film configured to filter blue light with wavelengths less than 455 nm, and may further reduce blue light with wavelengths less than 455 nm to protect eyes more while modulating reduced display brightness and reduce color aberration.

Abstract: Disclosed herein is a method for manufacturing a catalyst. The catalyst includes a mesoporous support and a plurality of metal nanoparticles dispersed and positioned in the mesopores of the mesoporous support. The method comprises the steps of: (a1)) allowing an organometallic precursor to be in contact with a mesoporous support, in which the organometallic precursor includes at least one material selected from the group consisting of ruthenium-containing compound, rhodium-containing compound and palladium-containing compound; and (a2) reducing the organometallic precursor in the presence of a supercritical fluid with a reductant, so that the organometallic precursor is reduced to the metal nanoparticles.

Abstract: A shielding layer outside a sensing region I of a CMOS image sensor includes a stack of a first monochromatic color filter layer and a second monochromatic color filter layer. Such a two-layered monochromatic color filter acts as a shielding layer, and the amount of black photoresist needed is decreased. Therefore, a process of CMOS image sensor fabrication is simplified and the cost of fabrication is decreased. The black pigment is prevented from remaining and causing contamination.

Abstract: An assessing mark of microlens array fabricated in a scribe line region includes two vertical line patterns arranged substantially in parallel with each other, and a horizontal line pattern connecting the vertical line patterns. The vertical line patterns and horizontal line pattern define an inner index path. When treated by baking process, the two vertical line patterns are fluidized due to heat and partially merge together from the horizontal line pattern of the assessing mark along the inner index path.

Abstract: A shielding layer outside a sensing region I of a CMOS image sensor includes a stack of a first monochromatic color filter layer and a second monochromatic color filter layer. Such a two-layered monochromatic color filter acts as a shielding layer, and the amount of black photoresist needed is decreased. Therefore, a process of CMOS image sensor fabrication is simplified and the cost of fabrication is decreased. The black pigment is prevented from remaining and causing contamination.

Abstract: An assessing mark of microlens array fabricated in a scribe line region includes two vertical line patterns arranged substantially in parallel with each other, and a horizontal line pattern connecting the vertical line patterns. The vertical line patterns and horizontal line pattern define an inner index path. When treated by baking process, the two vertical line patterns are fluidized due to heat and partially merge together from the horizontal line pattern of the assessing mark along the inner index path.

Abstract: A manufacturing method of a color filter film and an image sensor device is provided. The manufacturing method of the color filter film, comprises forming a color filter material layer over a substrate. Then, a segregation layer is formed over the color filter material layer to reduce a component of the color filter material layer from escaping. Thereafter, a patterning process is performed over the color filter material layer to form a color filter pattern, wherein a segregation layer is removed during the patterning process. Accordingly, since a segregation layer is formed over the color filter material layer before the patterning process is performed, the problem of contamination of the apparatus due to the escape of the component of the color filter material layer during the patterning process is reduced.