Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: A sprayer, comprising: a container, configured to contain liquid; a passage, comprising a first opening, a second opening, a resonator and a mesh, when the liquid is passed through the resonator, the liquid is emitted as a gas; a first optical sensor, configured to sense first optical data of at least portion of the mesh or at least portion of a surface of the container; and a processing circuit, configured to compute a foaming level of the mesh or of the surface according to the first optical data, and configured to determine whether the resonator should be turned off or not according to the foaming level. In another aspect, the processing circuit estimates a liquid level of the liquid but does not correspondingly turn off the resonator. By this way, the resonator may be turned on or turned off more properly and the liquid level may be more precisely estimated.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A foldable statue bag is disclosed. The foldable statue bag comprises a foldable bag body with an opening on a top end, and a statue integrated with the foldable bag body. The foldable bag body has two adjacent surfaces connect to a first fold line at opposite sides to form a recess or a protrusion, and the statue has a second fold line for folding so that the statue is received in the recess or protrude from the protrusion when the foldable bag body is folded, and the statue is expanded to form a three dimensional decoration when the foldable bag body is unfolded.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a dielectric layer; forming an aluminum layer on the dielectric layer; forming a platinum layer on the aluminum layer; performing a first etching process to remove part of the platinum layer and part of the aluminum layer for forming a patterned platinum layer; and performing a second etching process to remove part of the aluminum layer exposed by the patterned platinum layer and part of the dielectric layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a dielectric layer; forming an aluminum layer on the dielectric layer; forming a platinum layer on the aluminum layer; performing a first etching process to remove part of the platinum layer and part of the aluminum layer for forming a patterned platinum layer; and performing a second etching process to remove part of the aluminum layer exposed by the patterned platinum layer and part of the dielectric layer.

Abstract: An etching method for manufacturing MEMS devices is provided. The method includes steps of: providing a substrate including a first surface and a second surface opposite to the first surface, wherein a base structure, a sacrificial structure and at least one adhesion layer are arranged on the first surface of the substrate, the adhesion layer is disposed between the base structure and the sacrificial structure, the base structure is disposed between the adhesion layer and the substrate; performing a surface grinding process on the second surface of the substrate; performing a first plasma etching process by using a first mixed gas to remove the sacrificial structure, wherein the first mixed gas includes oxygen and a first nitrogen-based gas; and performing a second plasma etching process by using a second mixed gas to remove the adhesion layer, wherein the second mixed gas includes a second nitrogen-based base gas and a fluorine-based gas.

Abstract: A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas.

Abstract: A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas.

Abstract: A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.

Abstract: A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.