Patents by Inventor Hsin You S. Lee

Hsin You S. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features
    Patent number: 9484076
    Abstract: Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: November 1, 2016
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Leelean Shu, Yoshi Sato, Hsin You S. Lee
  • Systems and methods of memory and memory operation involving input latching, self-timing and/or other features
    Patent number: 9431079
    Abstract: Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from control circuitry.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 30, 2016
    Assignee: GSI Technology, Inc.
    Inventors: Leelean Shu, Yoshi Sato, Hsin You S. Lee
  • Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features
    Publication number: 20160005458
    Abstract: A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventors: Lee-Lean SHU, Chenming W. TUNG, Hsin You S. LEE
  • Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features
    Patent number: 9159391
    Abstract: Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 13, 2015
    Assignee: GSI Technology, Inc.
    Inventors: Leelean Shu, Yoshi Sato, Hsin You S. Lee
  • Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
    Patent number: 9135986
    Abstract: A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: September 15, 2015
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Chenming W. Tung, Hsin You S. Lee
  • SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, INCLUDING HIERARCHICAL AND/OR OTHER FEATURES
    Publication number: 20140219011
    Abstract: A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
    Type: Application
    Filed: November 26, 2013
    Publication date: August 7, 2014
    Applicant: GSI Technology Inc.
    Inventors: Lee-Lean SHU, Chenming W. TUNG, Hsin You S. LEE
  • Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
    Patent number: 8693236
    Abstract: A hierarchical sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line in hierarchy, and associated systems and methods are described. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line, and wherein the sectioned bit lines are arranged in hierarchical arrays. In other implementations, a hierarchical SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 8, 2014
    Assignee: GSI Technology, Inc.
    Inventors: LeeLean Shu, Chenming W. Tung, Hsin You S. Lee
  • Systems and methods of sectioned bit line memory arrays
    Patent number: 8593860
    Abstract: A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: November 26, 2013
    Assignee: GSI Technology, Inc.
    Inventors: LeeLean Shu, Chenming W. Tung, Hsin You S. Lee
  • SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS
    Publication number: 20130148414
    Abstract: A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Inventors: LeeLean Shu, Chenming W. Tung, Hsin You S. Lee
  • SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, INCLUDING HIERARCHICAL AND/OR OTHER FEATURES
    Publication number: 20130148415
    Abstract: A hierarchical sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line in hierarchy, and associated systems and methods are described. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line, and wherein the sectioned bit lines are arranged in hierarchical arrays. In other implementations, a hierarchical SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.
    Type: Application
    Filed: February 17, 2012
    Publication date: June 13, 2013
    Inventors: LeeLean Shu, Chenming W. Tung, Hsin You S. Lee