Patents by Inventor Hsin-Yuan Chiu

Hsin-Yuan Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240022857
    Abstract: A device for audio signal processing includes a main processor and two audio processors electrically connected with the main processor. Each audio processor corresponds to a channel of a stereo audio output. The main processor provides an indication signal for the two audio processors. Each audio processor generates a synchronization signal according to the indication signal and performs audio signal processing according to the synchronization signal. The synchronization signals begin simultaneously and have the same frequencies that equal a sampling frequency. Each synchronization signal includes at least one pulse, and a start of each pulse of each synchronization signal is aligned in time with a start of a pulse of the indication signal. The audio signal processing performed by each audio processor begins at an end of one of the at least one pulse in the synchronization signal corresponding to the audio processor.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Hsin-Yuan CHIU, Chia-Ling Hsieh
  • Publication number: 20230237985
    Abstract: An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 27, 2023
    Inventors: HSIN-YUAN CHIU, HSIANG-YU YANG, YA-MIEN HSU
  • Patent number: 11699423
    Abstract: An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: July 11, 2023
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventors: Hsin-Yuan Chiu, Hsiang-Yu Yang, Ya-Mien Hsu
  • Patent number: 11601753
    Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 7, 2023
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Hsin-Yuan Chiu, Tsung-Fu Lin
  • Publication number: 20220400341
    Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.
    Type: Application
    Filed: June 10, 2021
    Publication date: December 15, 2022
    Applicant: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Hsin-Yuan Chiu, Tsung-Fu Lin
  • Patent number: 11489499
    Abstract: A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 1, 2022
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventors: Tsung-Fu Lin, Hsin-Yuan Chiu
  • Patent number: 11368130
    Abstract: A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: June 21, 2022
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Hsin-Yuan Chiu, Hsiang-Yu Yang
  • Patent number: 10542345
    Abstract: A virtual bass generating circuit used in a speaker is used to filter out a high frequency part of an audio signal to generate a low passed audio signal, generates an even and odd audio signals respectively having even and odd harmonics of the low passed audio signal according to the low passed audio signal, subtracts an amplified low passed audio signal from an addition of an amplified even audio signal and an amplified odd audio signal to generate a first calculated audio signal, filters out a low frequency part and a high frequency part of the first calculated audio signal to generate a band passed audio signal, and adds the band passed audio signal and the audio signal to generate a second calculated audio signal with enhanced even and odd harmonics of the audio signal.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: January 21, 2020
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Hsin-Yuan Chiu, Tsung-Fu Lin
  • Publication number: 20190238979
    Abstract: A virtual bass generating circuit used in a speaker is used to filter out a high frequency part of an audio signal to generate a low passed audio signal, generates an even and odd audio signals respectively having even and odd harmonics of the low passed audio signal according to the low passed audio signal, subtracts an amplified low passed audio signal from an addition of an amplified even audio signal and an amplified odd audio signal to generate a first calculated audio signal, filters out a low frequency part and a high frequency part of the first calculated audio signal to generate a band passed audio signal, and adds the band passed audio signal and the audio signal to generate a second calculated audio signal with enhanced even and odd harmonics of the audio signal.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 1, 2019
    Inventors: HSIN-YUAN CHIU, TSUNG-FU LIN
  • Patent number: 9325283
    Abstract: An exemplary embodiment of the present disclosure illustrates a modulation method for a switching modulator. Firstly, a data signal is received. Then, a first output signal at a first output side of the switching modulator and a second output signal at a second output side of the switching modulator are generated according to the data signal received, wherein the first output signal is an addition signal of a first pulse signal and the data signal, the second output signal is a second pulse signal, the first pulse signal and the second pulse signal are aligned to a same pulse width, and the pulse width equals to a minimum resolution of the switching modulator.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: April 26, 2016
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Hsin-Yuan Chiu
  • Publication number: 20160079938
    Abstract: An exemplary embodiment of the present disclosure illustrates a modulation method for a switching modulator. Firstly, a data signal is received. Then, a first output signal at a first output side of the switching modulator and a second output signal at a second output side of the switching modulator are generated according to the data signal received, wherein the first output signal is an addition signal of a first pulse signal and the data signal, the second output signal is a second pulse signal, the first pulse signal and the second pulse signal are aligned to a same pulse width, and the pulse width equals to a minimum resolution of the switching modulator.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 17, 2016
    Inventor: HSIN-YUAN CHIU
  • Publication number: 20090054211
    Abstract: The trampoline contains a flexible jumping bed enclosed by a closed frame supported by a number of legs on the ground. A cushion element such as a spring, a rubber block, or a hydraulic or air buffering device is provided at each connection between the frame and the legs. The cushion element absorbs part of the downward force exerted on the frame and the legs so that an extended operation life of the trampoline is achieved.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 26, 2009
    Inventor: HSIN-YUAN CHIU
  • Patent number: 5943709
    Abstract: A swimming pool assembly includes a plurality of connectors, a plurality of struts, and a plurality of horizontal poles of a rhombic cross-section. After connecting the horizontal poles to engagement slots of the connectors, the structural strength of the swimming pool assembly can be considerably increased. Spring retaining pin elements are disposed inside the horizontal poles at both ends to engage positioning poles of the connectors so as to achieve firm connection. The connectors are further provided with canopy pole insert holes for mounting a canopy framework. The canopy framework can be formed by utilizing a plurality of canopy poles, a connecting tube seat, and a canopy. A sprinkling structure including L-shaped bent pipes disposed inside the engagement slots of the connectors can further be installed on the swimming pool framework.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: August 31, 1999
    Inventor: Hsin-Yuan Chiu