Abstract: A structure of manufacture of a semiconductor die on a lead-on-chip (LOC) packaging using a flexible copper plated tape and a standard lead frame is disclosed. A semiconductor die with bonding pads in the center is interconnected to a flexible copper plated tape by copper trace, solder bumps, or gold bump. The flexible copper plated tape is then placed on top of and attached to a standard lead frame. The configuration of a flexible copper plated tape, such material includes polymide tape, matches the configuration of a lead frame that allows the use of a standard outer lead frame. The configuration of a polymide tape provides greater flexibility in the placement of bonding pads anywhere on a semiconductor die without limiting the bonding pads to be placed in the center of a semiconductor die.

Abstract: A manufacturing plant is described for producing semiconductors that will function at a low production level during the initial phase. The plant can be expanded to provide a greater production volume with minimum additional investment, minimum disruption to the existing manufacturing line, and can be done quickly at minimum cost. Also described is a method for building a manufacturing plant for integrated circuit devices that can be operated at a low level during the initial phase, and provides for an efficient and rapid expansion to a higher level of manufacturing with minimum cost, and disruption to the existing line.

Abstract: The invention relates to a radiation-hardened (R-H) bulk CMOS process which is compatible with DRAM production and a specific gated isolation structure (GIS). The GIS structure consists of a novel oxide-silicon nitride-oxynitride gate insulator and a LPCVD polysilicon gate. A simple but automatically generating process for creating GIS directly from an original non-R-H device is also described. This generating process is fast and can revise any commercial products to a R-H version. The GIS is always shunted to Vss potential of the circuit chip to assure R-H capability. The grounded GIS structure replaces conventional LOCOS field oxide, which suffers from large threshold voltage shift when exposed to irradiation. Radiation resistance of this gated isolation structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuits (.ltoreq.2um design rule).

Abstract: The invention relates to a radiation hardened (R-H) bulk complementary metal oxide semiconductor (CMOS) isolation structure and a process for its formation. The isolation structure may be automatically generated from the original thin oxide layer of any commercial product by computer aided design and basically comprises a grounded MOS gate surrounding the active areas. The grounded MOS gate replaces the conventional LOCOS field oxide and consists of novel oxide-silicon nitride-oxynitride gate insulator and a CVD polysilicon film. The radiation resistance of this gated isolated structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuit (.ltoreq.2 .mu.m design rule).