Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.

Abstract: A semiconductor structure is provided. A logic cell includes a first transistor in a first active region, a second gate electrode and a third gate electrode on opposite sides of the first transistor, a second transistor in a second active region, and a first isolation structure and a second isolation structure on opposite edges of the second active region. The first transistor includes a first gate electrode extending in a first direction. The second and third gate electrodes extend in the first direction, and the first and second isolation structures extend in the first direction. The second transistor and the first transistor share the first gate electrode. The first isolation structure is aligned with the second gate structure in the first direction, and the second isolation structure is aligned with the third gate structure in the first direction.

Abstract: A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.