Abstract: A short pulse generating circuit including a pulse generating circuit, an actuation control circuit and a delay control circuit is provided. The pulse generating circuit is electrically coupled to a switch, which is coupled to a power. When the power is turned on, the power causes the pulse generating circuit to generate a long pulse. The actuation control circuit is electrically coupled to the power and the pulse generating circuit. When the power is turned on, the actuation control circuit controls a voltage level of each output of the pulse generating circuit to a fixed value. The delay control circuit is electrically coupled to the pulse generating circuit. When the switch is turned on, the power controls the delay control circuit to change the voltage level of each output of the pulse generating circuit to generate a short pulse output.

Abstract: A short pulse generating circuit including a pulse generating circuit, an actuation control circuit and a delay control circuit is provided. The pulse generating circuit is electrically coupled to a switch, which is coupled to a power. When the power is turned on, the power causes the pulse generating circuit to generate a long pulse. The actuation control circuit is electrically coupled to the power and the pulse generating circuit. When the power is turned on, the actuation control circuit controls a voltage level of each output of the pulse generating circuit to a fixed value. The delay control circuit is electrically coupled to the pulse generating circuit. When the switch is turned on, the power controls the delay control circuit to change the voltage level of each output of the pulse generating circuit to generate a short pulse output.

Abstract: A discharge circuit for an electronic device includes an energy storage element, a plurality of switches and a plurality of discharge paths coupled to the energy storage element and the switches. If a system power of the electronic device is turned off, a first switch of the switches conducts a first discharge path of the discharge paths, and the energy storage element is discharged through the first discharge path. In response that a voltage of the energy storage element drops to a first threshold, a second switch of the switches conducts a second discharge path of the discharge paths, and the energy storage element is discharged through the first discharge path and the second discharge path.

Abstract: A discharge circuit for an electronic device includes an energy storage element, a plurality of switches and a plurality of discharge paths coupled to the energy storage element and the switches. If a system power of the electronic device is turned off, a first switch of the switches conducts a first discharge path of the discharge paths, and the energy storage element is discharged through the first discharge path. In response that a voltage of the energy storage element drops to a first threshold, a second switch of the switches conducts a second discharge path of the discharge paths, and the energy storage element is discharged through the first discharge path and the second discharge path.

Abstract: An image acquiring apparatus and image acquiring method are provided. The image acquiring apparatus includes an image sensor for outputting a plurality of first analog image signals corresponding to a plurality of pixels; an ADC for converting the plurality of first analog image signals to a plurality of digital image signals; a DAC for converting the plurality of digital image signals to a plurality of second analog image signals, wherein each of which has an actual voltage value; a comparing unit for respectively comparing the actual voltage values of the plurality of second analog image signals with a reference voltage value so as to generate a plurality of corresponding comparing results; a counting unit for adjusting a counting value according to each of the comparing results; and a control unit for determining whether to stop a scanning operation of the image acquiring apparatus or not according to the counting value.

Abstract: A peripheral connected with a host via a transmission interface, and a power control method applied to the peripheral includes the steps of: receiving signal data from the host via the transmission interface; generating a power control signal when determining that the host and the peripheral are indifferent statuses; and selectively switching on or switching off an input power of the peripheral according to the power control signal, so as to make the peripheral change its status.

Abstract: A duplex scan apparatus for generating scanned images of a resolution includes an ASIC, a first CCD, a second CCD, a first AFE, and a second AFE. The ASIC processes digital data at an ASIC timing and outputs a CCD timing, wherein the ASIC timing equals twice as the resolution. The first CCD scans the first face of a document and generates first analog data according to the CCD timing. The second CCD scans the second face of the document and generates second analog data according to the CCD timing. The first AFE converts the first analog data into first digital data and outputs a first data amount of data points of the digital data to the ASIC for processing. The second AFE converts the second analog data into second digital data and outputs a second data amount of data points of the digital data to the ASIC for processing.

Abstract: An image scanning apparatus having scan background includes an analog front end (AFE) processor, a logic circuit module, and a control module. The AFE processor is utilized for outputting an actual gray level value corresponding to a gray level value of a scan image of a scan target and the scan background. The logic circuit module is coupled to the AFE processor and utilized for comparing the actual gray level value with a reference gray level value and outputting a corresponding control signal. The control module is coupled to the logic circuit module and utilized for determining whether to stop a scanning operation according to the control signal.

Abstract: The present invention provides a key status detecting circuit for detecting key statuses of a plurality of key modules, wherein the key modules respectively include a plurality of key units. The key status detecting circuit includes a plurality of first logic units, a plurality of first signal registering units, a plurality of second logic units, a second signal registering unit, and a control unit. The key status detecting circuit provided by the present invention does not have to connect each key to different pins of the control unit respectively and does not have to have the control unit regularly poll a data bus to detect which key is pressed, and thus the pin amount and loading of the control unit can be reduced, and efficiency of the control unit can be improved.

Abstract: An image acquiring apparatus and image acquiring method are provided. The image acquiring apparatus includes an image sensor for outputting a plurality of first analog image signals corresponding to a plurality of pixels; an ADC for converting the plurality of first analog image signals to a plurality of digital image signals; a DAC for converting the plurality of digital image signals to a plurality of second analog image signals, wherein each of which has an actual voltage value; a comparing unit for respectively comparing the actual voltage values of the plurality of second analog image signals with a reference voltage value so as to generate a plurality of corresponding comparing results; a counting unit for adjusting a counting value according to each of the comparing results; and a control unit for determining whether to stop a scanning operation of the image acquiring apparatus or not according to the counting value.

Abstract: A duplex scan apparatus includes an ASIC for outputting timing, a first CCD, a second CCD, a first AFE, and a second AFE. The first CCD is for sensing the first face of the to-be-scanned document and outputting first image data according to the timing. The second CCD is for sensing the second face of the to-be-scanned document and outputting second image data according to the timing. The first AFE is for converting the first image data into first digital data and outputting the digital data to the ASIC for processing. The second AFE is for converting the second image data into second digital data and outputting the digital data to the ASIC for processing. A constant data amount corresponding to the timing is a sum of a first data amount of the first digital data and a second data amount of the second digital data.