Patents by Inventor Hsing-Wen Chang
Hsing-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240163987Abstract: A dimming circuit is configured to generate a dimming signal to control a brightness of a light emitting device. The brightness is correlated with a duty ratio of the dimming signal. The dimming circuit is configured to count a conduction time of the dimming signal according to a programmable period count code and a programmable brightness code, based upon a fundamental frequency, wherein when the conduction time is less than a conduction time lower limit, based upon a down conversion ratio, the dimming circuit reduces a frequency of the dimming signal according to the programmable period count code and the programmable brightness code, wherein the down conversion ratio is greater than 1 to an extent where a dimming conduction time is greater than or equal to a conduction time lower threshold.Type: ApplicationFiled: August 30, 2023Publication date: May 16, 2024Inventors: Chun-Wen Wang, Yi-Hua Chang, Hsing-Shen Huang
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Patent number: 11926678Abstract: Disclosed herein are composite polypeptide. According to various embodiments, the composite polypeptide includes a parent polypeptide and a metal binding motif capable of forming a complex with a metal cation. The composite polypeptide may be conjugated with a linker unit having a plurality of functional elements to form a multi-functional molecular construct. Alternatively, multiple composite polypeptides may be conjugated to a linker unit to form a molecular construct, or a polypeptide bundle. Linker units suitable for conjugating with the composite polypeptide having the metal binding motif are also disclosed.Type: GrantFiled: October 8, 2021Date of Patent: March 12, 2024Assignee: Immunwork Inc.Inventors: Tse-Wen Chang, Hsing-Mao Chu, Wei-Ting Tian, Yueh-Hsiang Yu
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Patent number: 10770144Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines; raise a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period; raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period; and raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period.Type: GrantFiled: February 15, 2019Date of Patent: September 8, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsing-Wen Chang, Yao-Wen Chang
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Publication number: 20200265896Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines; raise a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period; raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period; and raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Applicant: MACRONIX International Co., Ltd.Inventors: Hsing-Wen Chang, Yao-Wen Chang
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Patent number: 10741250Abstract: A non-volatile memory device driving method, applicable to a non-volatile memory device comprising a row decoder and a memory array, comprises: utilizing the row decoder to transmit multiple word line signals to multiple word lines of the memory array; according to an address, utilizing the row decoder to switch a selected word line signal of the multiple word line signals from a predetermined voltage level to a program voltage level; utilizing the row decoder to switch at least one support word line signal of the multiple word line signals from the predetermined voltage level to a first pass voltage level; when the selected word line signal is remained at the program voltage level, utilizing the row decoder to switch the at least one support word line signal from the first pass voltage level to a higher second pass voltage level.Type: GrantFiled: June 5, 2019Date of Patent: August 11, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsing-Wen Chang, Yao-Wen Chang, Chi-Yuan Chin
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Publication number: 20200243121Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: selecting a programmed word line, where the programmed word line has a plurality of segments respectively corresponding to a plurality of bit lines; providing a program voltage to a voltage receiving end of the programmed word line, and sequentially transmitting the program voltage to the segments; respectively providing a plurality of bit line voltages to the bit lines at a plurality of enable time points and turning on a string selection switch at a setting time point; and setting voltage values of the bit line voltages according to the segments corresponding to the bit lines, respectively, or setting the enable time points according to the segments corresponding to the bit lines, or setting the setting time point according to a voltage transmission delay of the programmed word line.Type: ApplicationFiled: January 30, 2019Publication date: July 30, 2020Applicant: MACRONIX International Co., Ltd.Inventors: Chu-Yung Liu, Hsing-Wen Chang, Yung-Hsiang Chen, Yao-Wen Chang
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Patent number: 9437303Abstract: A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.Type: GrantFiled: August 25, 2015Date of Patent: September 6, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Chu-Yung Liu, Hsing-Wen Chang, Yao-Wen Chang, Tao-Cheng Lu
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Patent number: 8929134Abstract: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.Type: GrantFiled: February 8, 2013Date of Patent: January 6, 2015Assignee: Macronix International Co., Ltd.Inventors: Chu Yung Liu, Hsing Wen Chang, Yao Wen Chang, Tao Cheng Lu
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Publication number: 20140254280Abstract: A method for programming memory cells includes applying a programming voltage to a selected memory cell in a memory cell array and a neighboring passing voltage to a neighboring memory cell next to the selected memory cell, increasing the programming voltage for programming the selected memory cell, and increasing the neighboring passing voltage for programming the selected memory cell.Type: ApplicationFiled: May 22, 2013Publication date: September 11, 2014Applicant: Macronix International Co., Ltd.Inventors: Hsing Wen Chang, Yao Wen Chang, Yuan-Peng Chao
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Publication number: 20140226411Abstract: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: CHU YUNG LIU, HSING WEN CHANG, YAO WEN CHANG, TAO CHENG LU
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Publication number: 20140126296Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A jth page buffer drives an (N*(j?1)+1)th bit line to an (N*j)th bit line during the enabling period, and one of an (i?1)th bit line and an (i+1)th bit line is not driven when an ith bit line is not driven, wherein j is an integer and 1?j?M, and i is an integer and 1<i<M*N.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: MACRONIX International Co., Ltd.Inventors: Hsing-Wen Chang, Yao-Wen Chang, Chu-Yung Liu
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Patent number: 8644081Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M?1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1?i?N.Type: GrantFiled: March 23, 2011Date of Patent: February 4, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Hsing-Wen Chang, Yao-Wen Chang, Chu-Yung Liu
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Patent number: 8605507Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence.Type: GrantFiled: January 12, 2012Date of Patent: December 10, 2013Assignee: Macronix International Co., Ltd.Inventors: Chuyung Liu, Hsing-Wen Chang, Yaowen Chang, Tao-Cheng Lu
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Patent number: 8547166Abstract: A temperature compensation circuit, applied on a metal oxide semiconductor (MOS) transistor, with a threshold voltage varying with respect to a temperature value of the MOS transistor, for having the MOS transistor corresponding to an equivalent threshold voltage substantially with a constant value throughout a temperature range, comprises a voltage generator. The voltage generator provides a voltage proportional to absolute temperature (VPTAT) to drive the body of the MOS transistor in such way that a variation of the threshold voltage due to temperature variation of the MOS transistor is substantially compensated with a variation of the threshold voltage due to body-source voltage variation of the MOS transistor, so that the MOS transistor corresponds to the equivalent threshold voltage that is temperature invariant.Type: GrantFiled: July 29, 2011Date of Patent: October 1, 2013Assignee: Macronix International Co., Ltd.Inventors: Ju-An Chiang, Hsing-Wen Chang
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Publication number: 20130182505Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicant: Macronix International Co., Ltd.Inventors: Chuyung Liu, Hsing-Wen Chang, Yaowen Chang, Tao-Cheng Lu
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Publication number: 20130027116Abstract: A temperature compensation circuit, applied on a metal oxide semiconductor (MOS) transistor, with a threshold voltage varying with respect to a temperature value of the MOS transistor, for having the MOS transistor corresponding to an equivalent threshold voltage substantially with a constant value throughout a temperature range, comprises a voltage generator. The voltage generator provides a voltage proportional to absolute temperature (VPTAT) to drive the body of the MOS transistor in such way that a variation of the threshold voltage due to temperature variation of the MOS transistor is substantially compensated with a variation of the threshold voltage due to body-source voltage variation of the MOS transistor, so that the MOS transistor corresponds to the equivalent threshold voltage that is temperature invariant.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ju-An Chiang, Hsing-Wen Chang
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Publication number: 20120243334Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M?1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1?i?N.Type: ApplicationFiled: March 23, 2011Publication date: September 27, 2012Applicant: Macronix International Co., Ltd.Inventors: Hsing-Wen CHANG, Yao-Wen CHANG, Chu-Yung LIU
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Patent number: 8004890Abstract: An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels.Type: GrantFiled: May 8, 2009Date of Patent: August 23, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Yao-Wen Chang, Tao-Cheng Lu, I-Chen Yang, Hsing-Wen Chang
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Publication number: 20110189836Abstract: A method for reducing leakage current of a semiconductor device includes supplying a substantially constant and non-zero bulk bias to a relatively low threshold voltage semiconductor device during formation of a conductive channel of the semiconductor device and during the formation of a non-conductive channel of the semiconductor device.Type: ApplicationFiled: February 4, 2010Publication date: August 4, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yuan-Peng Chao, Yao Wen Chang, Hsing Wen Chang, Che-Shih Lin
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Publication number: 20100284220Abstract: An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels.Type: ApplicationFiled: May 8, 2009Publication date: November 11, 2010Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yao-Wen Chang, Tao-Cheng Lu, I-Chen Yang, Hsing-Wen Chang