Patents by Inventor Hsing Ya Huo

Hsing Ya Huo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for reducing testing times on integrated circuit dies
    Patent number: 7492179
    Abstract: Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: February 17, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Chiu, Hsing-Ya Huo, Tsung-Yu Lee
  • Method and system for centrally-controlled semiconductor wafer correlation
    Patent number: 7403864
    Abstract: A centrally-controlled correlation system for testing a correlation wafer and comparing the testing results with the wafer's reference data that has been determined previously. The testing instructions and the correlation criteria are stored and transmitted from a central database. Such centrally-controlled correlation system improves the reliability of the correlation results and reduces the time to correlate a correlation wafer.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: July 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsing Ya Huo, Chung-Lin Hsieh, Tsung-Yu Lee, Yang Yen-Ni
  • Method and system for centrally-controlled semiconductor wafer correlation
    Publication number: 20080106278
    Abstract: A centrally-controlled correlation system for testing a correlation wafer and comparing the testing results with the wafer's reference data that has been determined previously. The testing instructions and the correlation criteria are stored and transmitted from a central database. Such centrally-controlled correlation system improves the reliability of the correlation results and reduces the time to correlate a correlation wafer.
    Type: Application
    Filed: November 6, 2006
    Publication date: May 8, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsing Ya Huo, Chung-Lin Hsieh, Tsung-Yu Lee, Yang Yen-Ni
  • Systems and methods for reducing testing times on integrated circuit dies
    Publication number: 20070236238
    Abstract: Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.
    Type: Application
    Filed: April 10, 2006
    Publication date: October 11, 2007
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Chiu, Hsing-Ya Huo, Tsung-Yu Lee