Abstract: A diode structure and a manufacturing method are disclosed. The diode structure includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and an epitaxy layer. The semiconductor substrate includes a first surface. The first semiconductor layer and the second semiconductor layer are extended toward the interior of the semiconductor substrate from the first surface by implanting a dopant. Both of the semiconductor types of the first semiconductor layer and the second semiconductor layer are opposite to the semiconductor type of the semiconductor substrate. The epitaxy layer is formed on the first surface, connected with the first semiconductor layer and the second semiconductor layer and extended outwardly from the first surface. The first semiconductor layer and the second semiconductor layer are connected with each other, continuously.

Abstract: A diode structure and a manufacturing method are disclosed. The diode structure includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and an epitaxy layer. The semiconductor substrate includes a first surface. The first semiconductor layer and the second semiconductor layer are extended toward the interior of the semiconductor substrate from the first surface by implanting a dopant. Both of the semiconductor types of the first semiconductor layer and the second semiconductor layer are opposite to the semiconductor type of the semiconductor substrate. The epitaxy layer is formed on the first surface, connected with the first semiconductor layer and the second semiconductor layer and extended outwardly from the first surface. The first semiconductor layer and the second semiconductor layer are connected with each other, continuously.

Abstract: A transient-voltage-suppression diode structure and a manufacturing method thereof are disclosed. The structure includes a P type base substrate, an N type epitaxial layer, a P+ type implant layer, an N+ type implant layer, a plurality of deep trench portions, an interlayer dielectric layer and a first metal layer. The N type epitaxial layer is disposed on the P type base substrate. The P+ type implant layer and the N+ type implant layer are embedded within the N type epitaxial layer. The deep trench portions pass through the N type epitaxial layer and are connected with the P type base substrate. The first metal layer is disposed on the interlayer dielectric layer and connected with the P+ type implant layer, the N+ type implant layer, and the deep trench portions. The deep trench portions connected with the first metal layer are configured to form a silicon controlled rectifier.

Abstract: A transient-voltage-suppression diode structure and a manufacturing method thereof are disclosed. The structure includes a substrate, an N? type epitaxial layer, a first metal layer, a first N+ type implant layer, a deep N+ type implant layer and plural polycrystalline plugs. The N? type epitaxial layer is disposed on the substrate. The first metal layer is disposed on the N? type epitaxial layer to form a working-voltage terminal. The first N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is connected with the working-voltage terminal. The deep N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is spaced apart from the first N+ type implant layer at a separation distance. The plural polycrystalline plugs are connected between the working-voltage terminal of the first metal layer and the deep N+ type implant layer.

Abstract: A transient-voltage-suppression diode structure and a manufacturing method thereof are disclosed. The structure includes a substrate, an N? type epitaxial layer, a first metal layer, a first N+ type implant layer, a deep N+ type implant layer and plural polycrystalline plugs. The N? type epitaxial layer is disposed on the substrate. The first metal layer is disposed on the N? type epitaxial layer to form a working-voltage terminal. The first N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is connected with the working-voltage terminal. The deep N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N? type epitaxial layer is spaced apart from the first N+ type implant layer at a separation distance. The plural polycrystalline plugs are connected between the working-voltage terminal of the first metal layer and the deep N+ type implant layer.