Patents by Inventor Hsiu-Jung Yen
Hsiu-Jung Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10686030Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.Type: GrantFiled: September 18, 2017Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
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Publication number: 20180026091Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.Type: ApplicationFiled: September 18, 2017Publication date: January 25, 2018Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
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Patent number: 9768243Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.Type: GrantFiled: July 5, 2013Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
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Patent number: 9478466Abstract: A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench.Type: GrantFiled: December 1, 2015Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang
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Publication number: 20160086856Abstract: A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench.Type: ApplicationFiled: December 1, 2015Publication date: March 24, 2016Inventors: Hsiu-Jung Yen, Jen-Pan Wang
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Patent number: 9231069Abstract: A method comprises forming a gate trench between a plurality of gate spacers over a substrate, forming a resistor trench over the substrate, depositing a first layer on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a second layer over the first layer, depositing a gate electrode layer over the second layer and applying a chemical mechanical polish process to the gate electrode layer until the gate electrode layer is removed from the resistor trench.Type: GrantFiled: June 23, 2015Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang
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Publication number: 20150295060Abstract: A method comprises forming a gate trench between a plurality of gate spacers over a substrate, forming a resistor trench over the substrate, depositing a first layer on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a second layer over the first layer, depositing a gate electrode layer over the second layer and applying a chemical mechanical polish process to the gate electrode layer until the gate electrode layer is removed from the resistor trench.Type: ApplicationFiled: June 23, 2015Publication date: October 15, 2015Inventors: Hsiu-Jung Yen, Jen-Pan Wang
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Patent number: 9093375Abstract: A semiconductor structure comprises a metal gate structure formed in a substrate, wherein the metal gate structure comprises a first film formed of a first material and formed on a bottom and sidewalls of a gate trench, a second film formed of a second material and formed over the first film and a gate electrode formed over the second film. The semiconductor structure further comprises a resistor structure formed in the substrate, where the resistor structure comprises a third film formed of the first material and formed on a bottom and sidewalls of a resistor trench and a fourth film formed of the second material and formed over the third film.Type: GrantFiled: March 15, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang
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Publication number: 20140264743Abstract: First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film.Type: ApplicationFiled: May 30, 2013Publication date: September 18, 2014Inventors: Hsiu-Jung Yen, Jen-Pan Wang
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Publication number: 20140264753Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.Type: ApplicationFiled: July 5, 2013Publication date: September 18, 2014Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
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Patent number: 8815679Abstract: First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film.Type: GrantFiled: May 30, 2013Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Jung Yen, Jen-Pan Wang