Patents by Inventor Hsiu-Lien Liao
Hsiu-Lien Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8692332Abstract: A structure of a strained-silicon transistor includes a PMOS disposed on a substrate, a silicon nitride layer positioned on the PMOS, and a compressive stress film disposed on the silicon nitride layer, wherein the silicon nitride has a stress between ?0.1 Gpa and ?3.2 Gpa, and the stress of the silicon nitride is smaller than the stress of the compressive stress layer.Type: GrantFiled: January 14, 2010Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Jei-Ming Chen, Hsiu-Lien Liao, Yu-Tuan Tsai, Teng-Chun Tsai
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Publication number: 20110169095Abstract: A structure of a strained-silicon transistor includes a PMOS disposed on a substrate, a silicon nitride layer positioned on the PMOS, and a compressive stress film disposed on the silicon nitride layer, wherein the silicon nitride has a stress between ?0.1 Gpa and ?3.2 Gpa, and the stress of the silicon nitride is smaller than the stress of the compressive stress layer.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Inventors: Jei-Ming Chen, Hsiu-Lien Liao, Yu-Tuan Tsai, Teng-Chun Tsai
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Publication number: 20110065245Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate and a source/drain region in the semiconductor substrate adjacent to two sides of the gate structure; covering a stress layer on the gate structure and the source/drain region; etching away the stress layer to form a plurality of openings with larger top and smaller bottom to expose surface of the gate structure and the source/drain region; forming a metal layer in the openings; and using the stress layer as a salicide block to react the metal layer with the gate structure and the source/drain region for forming a plurality of silicide layers.Type: ApplicationFiled: September 13, 2009Publication date: March 17, 2011Inventors: Jei-Ming Chen, Kuo-Chih Lai, Teng-Chun Tsai, Hsiu-Lien Liao
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Patent number: 7846804Abstract: A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.Type: GrantFiled: June 5, 2007Date of Patent: December 7, 2010Assignee: United Microelectronics Corp.Inventors: Hsiu-Lien Liao, Neng-Kuo Chen, Teng-Chun Tsai, Yi-Wei Chen
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Publication number: 20100304042Abstract: A method for forming super high stress layer is provided. First, a substrate is provided. Second, an ammonia-related pretreatment is performed on the substrate. The flow rate of ammonia is not less than s.c.c.m. and the high-frequency source power is set to be not less than 800 W. Later, the super high stress layer is formed on the substrate having undergone the ammonia-related pretreatment.Type: ApplicationFiled: May 31, 2009Publication date: December 2, 2010Inventors: Hsiu-Lien Liao, Teng-Chun Tsai, Jei-Ming Chen, Yu-Tuan Tsai, Chien-Chung Huang
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Patent number: 7651960Abstract: Preventing a chemical vapor deposition (CVD) chamber from particle contamination in which a higher low-frequency radio frequency (LFRF) power and longer process time are provided to vacate the chamber and perform a pre-heat process. Following that, a pre-oxide layer is formed on the chamber wall, while a high-frequency radio frequency bias is provided to the chamber. The high-power LFRF is continuously provided to the chamber to sustain the temperature of the chamber, and then a main oxide layer deposition process is performed. The method is able to form an oxide layer of better quality on a CVD chamber wall, so as to solve the particle problem in the prior art. Therefore, yield is improved and the maintenance cost is reduced.Type: GrantFiled: April 18, 2005Date of Patent: January 26, 2010Assignee: United Microelectronics Corp.Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao
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Patent number: 7588883Abstract: A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a hard mask, and the hydrogen concentration of the patterned silicon nitride layer is more than 1022 atoms/cm3. Thereafter, the conductive layer and the dielectric layer are etched utilizing the hard mask as a mask. Finally, an etching solution is utilized to remove the hard mask.Type: GrantFiled: May 9, 2006Date of Patent: September 15, 2009Assignee: United Microelectronics Corp.Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao
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Patent number: 7544603Abstract: A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the silicon nitride layer is increased.Type: GrantFiled: September 22, 2005Date of Patent: June 9, 2009Assignee: United Microelectronics Corp.Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao
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Publication number: 20080305600Abstract: A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.Type: ApplicationFiled: June 5, 2007Publication date: December 11, 2008Inventors: Hsiu-Lien Liao, Neng-Kuo Chen, Teng-Chun Tsai, Yi-Wei Chen
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Publication number: 20080242020Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Next, an inert gas treatment is performed to change a stress value of the stressed cap layer. Because the stress value of the stressed cap layer can be adjusted easily by means of the present invention, one stressed cap layer can be applied to both the N-type MOS transistor and the P-type MOS transistor.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Jei-Ming Chen, Neng-Kuo Chen, Hsiu-Lien Liao, Teng-Chun Tsai, Chien-Chung Huang, Shih-Wei Sun
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Publication number: 20080237662Abstract: A method of fabricating a semiconductor device is provided. A MOS transistor is formed on a substrate, and then a contact etching stop layer (CESL) is formed over the substrate. A first UV-curing process is performed to increase the stress of the CESL. A dielectric layer is formed on the CESL, and then a second UV-curing process is performed to increase the stress of the dielectric layer. A CMP process is conducted, and then a cap layer is formed on the dielectric layer.Type: ApplicationFiled: May 9, 2008Publication date: October 2, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: HSIU-LIEN LIAO, NENG-KUO CHEN, JEI-MING CHEN, TENG-CHUN TSAI, CHIEN-CHUNG HUANG
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Publication number: 20080237658Abstract: A method of fabricating a semiconductor device is provided. A MOS transistor is formed on a substrate, and then a contact etching stop layer (CESL) is formed over the substrate. A first UV-curing process is performed to increase the stress of the CESL. A dielectric layer is formed on the CESL, and then a second UV-curing process is performed to increase the stress of the dielectric layer. A CMP process is conducted, and then a cap layer is formed on the dielectric layer.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsiu-Lien Liao, Neng-Kuo Chen, Jei-Ming Chen, Teng-Chun Tsai, Chien-Chung Huang
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Publication number: 20080206943Abstract: A method of fabricating CMOS transistor is disclosed. Initially, a semiconductor substrate having at least a first active area and a second active area is provided. A high-strained thin film is formed on the semiconductor substrate, the first active area, and the second active area. Thereafter, a mask is formed to cover a part of the high-strained thin film, which is disposed on the first active area. An implantation is performed to implant dopants into the part of the high-strained thin film on the second active area and to modify the stress status thereof. After that, the mask is removed and a rapid thermal annealing process is performed. Then, the high-strained thin film is removed and the method of the present invention is accomplished.Type: ApplicationFiled: February 26, 2007Publication date: August 28, 2008Inventors: Jei-Ming Chen, Neng-Kuo Chen, Hsiu-Lien Liao, Teng-Chun Tsai
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Publication number: 20080188091Abstract: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.Type: ApplicationFiled: March 6, 2008Publication date: August 7, 2008Inventors: SHAO-TA HSU, Teng-Chun Tsai, Neng-Kuo Chen, Hsiu-Lien Liao, Cheng-Han Wu, Wen-Han Hung
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Publication number: 20080185655Abstract: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.Type: ApplicationFiled: February 2, 2007Publication date: August 7, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shao-Ta Hsu, Teng-Chun Tsai, Neng-Kuo Chen, Hsiu-Lien Liao, Cheng-Han Wu, Wen-Han Hung
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Publication number: 20070264836Abstract: A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a hard mask, and the hydrogen concentration of the patterned silicon nitride layer is more than 1022 atoms/cm3. Thereafter, the conductive layer and the dielectric layer are etched utilizing the hard mask as a mask. Finally, an etching solution is utilized to remove the hard mask.Type: ApplicationFiled: May 9, 2006Publication date: November 15, 2007Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao
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Publication number: 20070105292Abstract: A method for fabricating high tensile stress film and strained-silicon transistors. First, a semiconductor substrate is provided and a gate, at least a spacer, and a source/drain region are formed on the semiconductor substrate. Next, n deposition processes are performed to form n layers of high tensile stress film over the surface of the gate and the source/drain region, in which each high tensile stress film is treated with a heat treatment process and n is greater than or equal to two.Type: ApplicationFiled: November 7, 2005Publication date: May 10, 2007Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao, Chien-Chung Huang
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Publication number: 20070066022Abstract: A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the silicon nitride layer is increased.Type: ApplicationFiled: September 22, 2005Publication date: March 22, 2007Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao
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Publication number: 20060234518Abstract: Preventing a chemical vapor deposition (CVD) chamber from particle contamination in which a higher low-frequency radio frequency (LFRF) power and longer process time are provided to vacate the chamber and perform a pre-heat process. Following that, a pre-oxide layer is formed on the chamber wall, while a high-frequency radio frequency bias is provided to the chamber. The high-power LFRF is continuously provided to the chamber to sustain the temperature of the chamber, and then a main oxide layer deposition process is performed. The method is able to form an oxide layer of better quality on a CVD chamber wall, so as to solve the particle problem in the prior art. Therefore, yield is improved and the maintenance cost is reduced.Type: ApplicationFiled: April 18, 2005Publication date: October 19, 2006Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao