Patents by Inventor Hsiu-Wen Ho
Hsiu-Wen Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11362464Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.Type: GrantFiled: September 22, 2020Date of Patent: June 14, 2022Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Patent number: 11316305Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.Type: GrantFiled: September 22, 2020Date of Patent: April 26, 2022Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Publication number: 20220052489Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a pair of first contacts and eight second contacts. The pair of first contacts is a pair of differential signal contacts. The second contacts are arranged around the pair of first contacts. Two of the second contacts are arranged along a straight line perpendicular to a connecting line of the pair of first contacts. The position distribution and electrical properties of the other six of the second contacts are symmetrical to each other relative to the straight line.Type: ApplicationFiled: September 22, 2020Publication date: February 17, 2022Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Publication number: 20220052488Abstract: A contact arrangement, including multiple contacts, is provided. The contacts are staggered. Some of the contacts form at least one contact group. The at least one contact group includes a first contact and six second contacts. The second contacts are arranged around the first contact. When the first contact is a power contact or a ground contact, the second contacts are signal contacts. When the first contact is a signal contact, three of the second contacts are power contacts or ground contacts and are not adjacent to each other.Type: ApplicationFiled: September 22, 2020Publication date: February 17, 2022Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.Inventors: Nai-Shung Chang, Yun-Han Chen, Hsiu-Wen Ho, Tsai-Sheng Chen, Chang-Li Tan, Chun-Yen Kang, Hsin-Kuan Wu
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Patent number: 10568199Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Patent number: 10568200Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Patent number: 10568198Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: GrantFiled: November 1, 2017Date of Patent: February 18, 2020Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.Inventors: Nai-Shung Chang, Tsai-Sheng Chen, Chang-Li Tan, Yun-Han Chen, Hsiu-Wen Ho
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Publication number: 20180374790Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: ApplicationFiled: November 3, 2017Publication date: December 27, 2018Inventors: Nai-Shung CHANG, Tsai-Sheng CHEN, Chang-Li TAN, Yun-Han CHEN, Hsiu-Wen HO
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Publication number: 20180376582Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: ApplicationFiled: November 1, 2017Publication date: December 27, 2018Inventors: Nai-Shung CHANG, Tsai-Sheng CHEN, Chang-Li TAN, Yun-Han CHEN, Hsiu-Wen HO
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Publication number: 20180374789Abstract: A circuit substrate and a semiconductor package structure are provided. The circuit substrate includes a body and a via hole array. The via hole array includes via hole column units periodically arranged along a first direction. Each via hole column unit includes first to sixth via holes passing through the body and electrically connected to a capacitor. Any two adjacent via holes of the first to sixth via holes transmit power and ground signals. The sixth via hole of one of the via hole column units is adjacent to the first via hole of another one of the via hole column units, which is adjacent to the one of the via hole column units. The sixth via hole of one of the via hole column units and the first via hole of another one of the via hole column units transmit power and ground signals.Type: ApplicationFiled: November 3, 2017Publication date: December 27, 2018Inventors: Nai-Shung CHANG, Tsai-Sheng CHEN, Chang-Li TAN, Yun-Han CHEN, Hsiu-Wen HO
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Patent number: 6498759Abstract: A system can produce a suitable voltage for powering the memory modules plugged into the memory module slots of a motherboard. A power-good signal is issued when the motherboard is powered up. A power safety device on the motherboard then issues a 2.5V to the memory module slot. If DDR DRAM type of memory modules are not detected after a while, the power safety device will turn off the 2,5V supply and provide a 3.3V, which is suitable for SDRAM type memory modules.This invention avoids sending a 3.3V to DDR DRAM modules, thereby burning the memory chip. The presence of DDR DRAM modules can be detected by a general-purpose purpose input/output port through accessing the recorded data in the EEPROM of the memory module. Alternatively, memory module type can be determined by sending out a low-current pulse signal to the memory module slot. Hence, a suitable voltage source is automatically provided to power the memory modules in the slots.Type: GrantFiled: December 29, 2000Date of Patent: December 24, 2002Assignee: VIA Technologies, Inc.Inventors: Nai-Shung Chang, Ching-Fu Chuang, Hsiu-Wen Ho
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Patent number: 6384346Abstract: A trace layout of a printed circuit board (PCB) is provided with a north bridge, at least a peripheral component interconnect (PCI) slot, and an accelerate graphics port (AGP) slot. The PCB includes at least a first trace layer and a second trace layer under the first trace layer. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces, and a number of second traces. The first traces are used for connecting the north bridge to the PCI slot while the second traces are used to connect the north bridge to the AGP slot. Some of the first traces are on the second trace layer under the AGP slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer and the other of the second traces are on the second trace layer.Type: GrantFiled: October 12, 2000Date of Patent: May 7, 2002Assignee: Via Technologies, Inc.Inventors: Nai-Shung Chang, Ching-Fu Chuang, Hsiu-Wen Ho, Chia-Hsing Yuo, Shu-Hui Chen
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Publication number: 20020003740Abstract: A system can produce a suitable voltage for powering the memory modules plugged into the memory module slots of a motherboard. A power-good signal is issued when the motherboard is powered up. A power safety device on the motherboard then issues a 2.5V to the memory module slot. If DDR DRAM type of memory modules are not detected after a while, the power safety device will turn off the 2.5V supply and provide a 3.3V, which is suitable for SDRAM type memory modules. This invention avoids sending a 3.3V to DDR DRAM modules, thereby burning the memory chip. The presence of DDR DRAM modules can be detected by a general-purpose input/output port through accessing the recorded data in the EEPROM of the memory module. Alternatively, memory module type can be determined by sending out a low-current pulse signal to the memory module slot. Hence, a suitable voltage source is automatically provided to power the memory modules in the slots.Type: ApplicationFiled: December 29, 2000Publication date: January 10, 2002Inventors: Nai-Shung Chang, Ching-Fu Chuang, Hsiu-Wen Ho