Patents by Inventor Hsu-Shui Liu

Hsu-Shui Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11430108
    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Publication number: 20220261001
    Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Inventors: Cheng-Kang HU, Cheng-Hung CHEN, Yan-Han CHEN, Feng-Kuang WU, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
  • Patent number: 11402761
    Abstract: A lithography method to pattern a first semiconductor wafer is disclosed. An optical mask is positioned over the first semiconductor wafer. A first region of the first semiconductor wafer is patterned by directing light from a light source through transparent regions of the optical mask. A second region of the first semiconductor wafer is patterned by directing energy from an energy source to the second region, wherein the patterning of the second region comprises direct-beam writing.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tsiao-Chen Wu, Chi-Ming Yang, Hsu-Shui Liu
  • Publication number: 20220185512
    Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: Tsung-Sheng KUO, Hsu-Shui LIU, Jiun-Rong PAI, Yang-Ann CHU, Chieh-Chun LIN, Shine CHEN
  • Publication number: 20220189792
    Abstract: An apparatus for handling wafer carriers in a semiconductor fabrication facility (FAB) is disclosed. In one example, the apparatus includes: a table configured to receive a wafer carrier having a first door and operable to hold a plurality of wafers; an opening mechanism configured to open the first door of the wafer carrier; and a door storage space configured to store the first door. The apparatus may be either located on a floor of the FAB or physically coupled to a ceiling of the FAB.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: Tsung-Sheng KUO, Yang-Ann CHU, Alan YANG, Vic HUANG, Hsu-Shui LIU, Jiun-Rong PAI
  • Patent number: 11334080
    Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Kang Hu, Cheng-Hung Chen, Yan-Han Chen, Feng-Kuang Wu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 11299302
    Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Yang-Ann Chu, Chieh-Chun Lin, Shine Chen
  • Patent number: 11270900
    Abstract: An apparatus for handling wafer carriers in a semiconductor fabrication facility (FAB) is disclosed. In one example, the apparatus includes: a table configured to receive a wafer carrier having a first door and operable to hold a plurality of wafers; an opening mechanism configured to open the first door of the wafer carrier; and a door storage space configured to store the first door. The apparatus may be either located on a floor of the FAB or physically coupled to a ceiling of the FAB.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Alan Yang, Vic Huang, Hsu-Shui Liu, Jiun-Rong Pai
  • Publication number: 20220059415
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20220059376
    Abstract: A system and method for defect detection in a hole array on a substrate is disclosed herein. In one embodiment, a method for defect detection in a hole array on a substrate, includes: scanning a substrate surface using at least one optical detector, generating at least one image of the substrate surface; and analyzing the at least one image to detect defects in the hole array on the substrate surface based on a set of predetermined criteria.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 24, 2022
    Inventors: Becky LIAO, Sheng-Hsiang CHUANG, Cheng-Kang HU, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
  • Publication number: 20220059393
    Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.
    Type: Application
    Filed: August 20, 2020
    Publication date: February 24, 2022
    Inventors: Chien-Fa LEE, Chin-Lin CHOU, Shang-Ying TSAI, Shou-Wen KUO, Kuei-Sung CHANG, Jiun-Rong PAI, Hsu-Shui LIU, Chun-wen CHENG
  • Publication number: 20210370363
    Abstract: A cleaning apparatus, method, and dry chamber are provided for cleaning a wafer carrier that holds wafers as part of a semiconductor fabrication process. The cleaning apparatus includes a wet chamber that receives the wafer carrier to be washed and a reservoir in fluid communication with the wet chamber. The reservoir stores a cleaning liquid that is introduced to the wafer carrier within the wet chamber during a washing operation, and a dry chamber is spaced apart from the wet chamber. The dry chamber receives the wafer carrier after the wafer carrier is washed in the wet chamber and holds the wafer carrier during a drying operation. A transport system transports the wafer carrier between the wet chamber and the dry chamber during a cleaning process.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Eason Chen, Yi-Fam Shiu, Sung-Chun Yang, Hsu-Shui Liu, Yang-Ann Chu, Jiun-Rong Pai
  • Publication number: 20210364930
    Abstract: A lithography method to pattern a first semiconductor wafer is disclosed. An optical mask is positioned over the first semiconductor wafer. A first region of the first semiconductor wafer is patterned by directing light from a light source through transparent regions of the optical mask. A second region of the first semiconductor wafer is patterned by directing energy from an energy source to the second region, wherein the patterning of the second region comprises direct-beam writing.
    Type: Application
    Filed: March 2, 2021
    Publication date: November 25, 2021
    Inventors: Tsiao-Chen Wu, Chi-Ming Yang, Hsu-Shui Liu
  • Patent number: 11171065
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Patent number: 11158531
    Abstract: An operating method of a wafer cassette handling apparatus includes at least the following steps. A stage that carries a wafer cassette is moved into a main body of a wafer cassette handling apparatus to open a cassette door of the wafer cassette. The stage that carries the wafer cassette is moved out of the main body after the cassette door is opened. A wafer is extracted from the wafer cassette and transferred to a processing system. Another operating method and a wafer cassette handling apparatus are also provided.
    Type: Grant
    Filed: December 15, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Sheng Kuo, Hsuan Lee, Hsu-Shui Liu, Jiun-Rong Pai, Chih-Hung Huang, Yang-Ann Chu
  • Patent number: 11152238
    Abstract: In an embodiment, a system includes a profiler configured to detect variations along a surface of a semiconductor stage; and a jig configured to move the profiler along an axis over the semiconductor stage.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sheng-Hsiang Chuang, Cheng-Hung Chen
  • Patent number: 11120539
    Abstract: A method for scanning and analyzing a surface, the method comprising: receiving a piece of equipment with a target surface for inspection; receiving an input from a user; determining at least one scan parameter based on the user input; scanning the target surface using an optical detector in accordance with the at least one scan parameter; generating an image of the target surface; correcting the image of the target surface to remove at least one undesired feature to generate a corrected image based on the at least one scan parameter; and analyzing the corrected image to determine at least one geometric parameter of the target surface.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiang Chuang, Jiao-Rou Liao, Cheng-Kang Hu, Shou-Wen Kuo, Jiun-Rong Pai, Hsu-Shui Liu
  • Publication number: 20210257247
    Abstract: A system and method for cleaning and inspecting ring frames is disclosed here. In one embodiment, a ring frame processing system includes: a cleaning station configured to remove a first tape on a first surface of a ring frame using a first blade, clean first adhesive residues from the first tape on the first surface of the ring frame using a first wheel brush, and remove second adhesive residues from a second tape on a second surface of the ring frame using a second blade; and an inspection station, wherein the inspection station comprises an automated optical inspection system configured to determine the cleanness of the first and second surfaces of the ring frame after cleaning.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Chien-Fa LEE, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO, Jian-Hung CHENG, M.C. LIN, C.C. CHIEN, Hsuan LEE, Boris HUANG
  • Publication number: 20210242085
    Abstract: Some embodiments relate to a processing tool for processing a singulated semiconductor die. The tool includes an evaluation unit, a drying unit, and a die wipe station. The evaluation unit is configured to subject the singulated semiconductor die to a liquid to detect flaws in the singulated semiconductor die. The drying unit is configured to dry the liquid from a frontside of the singulated semiconductor die. The die wipe station includes an absorptive drying structure configured to absorb the liquid from a backside of the singulated semiconductor die after the drying unit has dried the liquid from the frontside of the singulated semiconductor die.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 5, 2021
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Yang-Ann Chu
  • Publication number: 20210242043
    Abstract: An apparatus and method for debonding a pair of bonded wafers are disclosed herein. In some embodiments, the debonding apparatus, comprises: a wafer chuck having a preset maximum lateral dimension and configured to rotate the pair of bonded wafers attached to a top surface of the wafer chuck, a pair of circular plate separating blades including a first separating blade and a second separating blade arranged diametrically opposite to each other at edges of the pair of bonded wafers, wherein the first and the second separating blades are inserted between a first and a second wafers of the pair of bonded wafers, and at least two pulling heads configured to pull the second wafer upwardly so as to debond the second wafer from the first wafer.
    Type: Application
    Filed: December 2, 2020
    Publication date: August 5, 2021
    Inventors: Cheng-Fei Yu, Chang-Chen TSAO, Ting-Yau Shiu, Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai