Patents by Inventor Hsuan-I Wang

Hsuan-I Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240045317
    Abstract: A method includes forming a reflective multilayer over a substrate; depositing a first capping layer over the reflective multilayer, wherein the first capping layer is made of a ruthenium-containing material or a chromium-containing material; performing a treatment to the first capping layer to introduce nitrogen or fluorine into the first capping layer; forming an absorption layer over the first capping layer; and patterning the absorption layer.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Pei-Cheng HSU, Hsuan-I WANG, Hung-Yi TSAI, Bo-Wei SHIH, Ta-Cheng LIEN
  • Patent number: 10353285
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Yun-Yue Lin, Hsuan-Chen Chen, Hsuan-I Wang, Anthony Yen
  • Publication number: 20180292744
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN, Hsuan-Chen CHEN, Hsuan-I WANG, Anthony YEN
  • Publication number: 20180173093
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Pei-Cheng HSU, Hsin-Chang LEE, Yun-Yue LIN, Hsuan-Chen CHEN, Hsuan-I WANG, Anthony YEN
  • Patent number: 10001701
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Cheng Hsu, Hsin-Chang Lee, Yun-Yue Lin, Hsuan-Chen Chen, Hsuan-I Wang, Anthony Yen
  • Patent number: 6961797
    Abstract: According to the claimed invention, the computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, and a south bridge electrically connected to the north bridge, the south bridge having a general purpose serial input/output port. The computer also includes at least one peripheral device electrically connected to the south bridge and an interfacing circuit for providing a plurality of extended general purpose input/output ports, the interfacing circuit having a connection end electrically connected to the general purpose serial input/output port. When inputting a data signal from a general purpose input/output (GPIO) port, the data signal is transmitted to the general purpose serial input/output port through the connection end of the interfacing circuit.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: November 1, 2005
    Assignee: VIA Technologies Inc.
    Inventors: Chia-Hsing Yu, Hsuan-I Wang, Chi-Hsing Lin
  • Publication number: 20020169916
    Abstract: According to the claimed invention, the computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, and a south bridge electrically connected to the north bridge, the south bridge having a general purpose serial input/output port. The computer also includes at least one peripheral device electrically connected to the south bridge and an interfacing circuit for providing a plurality of extended general purpose input/output ports, the interfacing circuit having a connection end electrically connected to the general purpose serial input/output port. When inputting a data signal from a general purpose input/output (GPIO) port, the data signal is transmitted to the general purpose serial input/output port through the connection end of the interfacing circuit.
    Type: Application
    Filed: April 24, 2002
    Publication date: November 14, 2002
    Inventors: Chia-Hsing Yu, Hsuan-I Wang, Chi-Hsing Lin