Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

Abstract: The application discloses a method applied in a system. The method includes the following operations: determining a first statistics of a first signal and a second statistics of a second signal according to a power split ratio and a noise level of a relay node; relaying, by the relay node, the first signal according to the power split ratio, the first statistics and the second statistics to generate the second signal; and receiving, by a destination node, the second signal.

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

Abstract: The application discloses a method applied in a system. The method includes the following operations: determining a first statistics of a first signal and a second statistics of a second signal according to a power split ratio and a noise level of a relay node; relaying, by the relay node, the first signal according to the power split ratio, the first statistics and the second statistics to generate the second signal; and receiving, by a destination node, the second signal.

Abstract: The present disclosure provides a resource allocation method. The resource allocation method includes the following steps: selecting multiple first selected virtual nodes according to multiple virtual pheromonal trails on multiple virtual edges, in which the first selected virtual nodes forms at least one virtual tour, and the virtual tour includes multiple first virtual edges; updating the virtual pheromonal trails on the virtual edges according to virtual distances corresponding to the first virtual edges of the virtual tour; selecting multiple second selected virtual nodes according to the updated virtual pheromonal trails on the virtual edges, in which the second selected virtual nodes form at least one resulting virtual tour; allocating the resource blocks to selected user pairs according to the resulting virtual tour.

Abstract: A user pairing method is provided. The method includes the following steps: selecting a first uplink user device among the uplink set; selecting a first downlink user device among the downlink set; determining whether the first uplink channel gain corresponding to the first uplink user device is greater than a second uplink channel gain corresponding to the first downlink user device, to generate a first determination result; determining whether a first signal to noise plus interference ratio (SINR) perceived at the first downlink user device is greater than a first SINR threshold, to generate a second determination result; forming the first uplink user device and the first downlink user device as a first user pair in a full duplexing (FD) mode when the first determination result and the second first determination result are positive.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A method for radio frequency chain allocation. The method is utilized in a massive multiple-input multiple-output (MIMO) system. Specifically, a hybrid beamforming (HB) system in which the overall beamformer consists of a low-dimensional digital beamformer followed by an analog beamformer utilized the method to allocate RF chains to data streams. The total number of RF chains is not necessarily equal to the number of data streams to users.

Abstract: A precoding method is provided. The precoding method includes computing a relaxed beamforming matrix according to multiple desired channel correlation matrices and multiple interfering channel correlation matrices; computing an approximated beamforming matrix according to the relaxed beamforming matrix; computing multiple degradations corresponding to the data streams according to multiple relaxed beamforming vectors within the relaxed beamforming matrix and multiple approximated beamforming vectors within the approximated beamforming matrix; selecting a selected data stream index according to the degradations; decomposing a selected relaxed beamforming vector corresponding to the selected data stream index into a first vector and a second vector; and updating the approximated beamforming matrix according to the first vector and augmenting the approximated beamforming matrix according to the second vector, to obtain an updated-and-augmented beamforming matrix.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: The present disclosure provides a resource allocation method. The resource allocation method includes the following steps: selecting multiple first selected virtual nodes according to multiple virtual pheromonal trails on multiple virtual edges, in which the first selected virtual nodes forms at least one virtual tour, and the virtual tour includes multiple first virtual edges; updating the virtual pheromonal trails on the virtual edges according to virtual distances corresponding to the first virtual edges of the virtual tour; selecting multiple second selected virtual nodes according to the updated virtual pheromonal trails on the virtual edges, in which the second selected virtual nodes form at least one resulting virtual tour; allocating the resource blocks to selected user pairs according to the resulting virtual tour.

Abstract: A user pairing method is provided. The method includes the following steps: selecting a first uplink user device among the uplink set; selecting a first downlink user device among the downlink set; determining whether the first uplink channel gain corresponding to the first uplink user device is greater than a second uplink channel gain corresponding to the first downlink user device, to generate a first determination result; determining whether a first signal to noise plus interference ratio (SINR) perceived at the first downlink user device is greater than a first SINR threshold, to generate a second determination result; forming the first uplink user device and the first downlink user device as a first user pair in a full duplexing (FD) mode when the first determination result and the second first determination result are positive.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A method for radio frequency chain allocation. The method is utilized in a massive multiple-input multiple-output (MIMO) system. Specifically, a hybrid beamforming (HB) system in which the overall beamformer consists of a low-dimensional digital beamformer followed by an analog beamformer utilized the method to allocate RF chains to data streams. The total number of RF chains is not necessarily equal to the number of data streams to users.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A method and a system for cache placement of base station and a corresponding base station are provided. The method for cache placement of base station includes the following steps. A dynamic moving information of a mobile device is obtained. A popularity of a file is generated according to the dynamic traveling information of the mobile device. A cache placement of at least one base station is determined according to the popularity. The file is transmitted to the at least one base station according to the cache placement for downloading by the mobile device.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: The disclosure is directed to a method and apparatus for D2D communication in a wireless communication system and related apparatuses using the same. In one of the exemplary embodiments, a proposed method may include determining whether to performing a D2D transmission and a cellular transmission simultaneously in a resource block allocated in a cellular uplink time slot; if a cellular uplink transmission rate in addition to a D2D transmission rate is greater than or equal to a maximum cellular UL transmission rate: performing the D2D transmission and the cellular transmission simultaneously; and adjusting a power of the D2D transmission and a power of the cellular transmission to maximize an overall transmission rate which is the cellular UL transmission rate in addition to the D2D transmission rate.

Abstract: A coordinated multipoint (CoMP) transmission and reception method and a CoMP transmission and reception base station are provided. The CoMP transmission and reception method include the following steps. Forming a plurality of base stations into a CoMP set. Calculating a corresponding Doppler shift value between each of the base stations in the CoMP set and a mobile device respectively. Performing, by each of the base stations in the CoMP set, a Doppler compensation on a reference signal according to the corresponding Doppler shift value to generate a corresponding Doppler compensated reference signal, determining whether a corresponding carrier frequency offset (CFO) value of the corresponding Doppler compensated reference signal is converged, and if all of the CFO values are converged, then each of the base stations in the CoMP set performs a frequency correction according to the corresponding CFO value.

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.