Patents by Inventor Hsuan Lee

Hsuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735471
    Abstract: A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ta Yu, Kai-Hsuan Lee, Sai-Hooi Yeong, Yen-Chieh Huang, Feng-Cheng Yang
  • Patent number: 11735641
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien Ning Yao, Kai-Hsuan Lee, Sai-Hooi Yeong, Wei-Yang Lee, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20230261068
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Kai-Hsuan LEE, Shih-Che LIN, Po-Yu HUANG, Shih-Chieh WU, I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20230259024
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, selectively exposing the photoresist layer to an EUV radiation, and developing the selectively exposed photoresist layer. The photoresist layer has a composition including a solvent and a photo-active compound dissolved in the solvent and composed of a molecular cluster compound incorporating hexameric tin and two chloro ligands.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 17, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Po-Hsuan LEE, An-Yun LU, Kuang-Ting CHEN, Po-Hsiung CHEN, Burn Jeng LIN
  • Publication number: 20230244501
    Abstract: The disclosure discloses a program killing system including a memory and a processor. The processor obtains instructions from the memory to perform the following steps: collecting use counts, use times, and a first use order of programs; generating a first candidate list based on the plurality of use counts and the use times, generating a second candidate list based on the use counts, and generating a third candidate list based on the first use order; collecting a second use order of the programs in an operation time to generate an operation list; comparing each of the first candidate list, the second candidate list, and the third candidate list with the operation list to produce a comparison result; and outputting one of the first candidate list, the second candidate list, or the third candidate list as a judgment list according to the comparison result.
    Type: Application
    Filed: October 7, 2022
    Publication date: August 3, 2023
    Inventors: Yun-Hsuan LEE, Tse-Chih LIN
  • Patent number: 11712330
    Abstract: A vascular graft deployment tool may include a grip, an elongated mandrel positioned distal of the grip, a vascular graft, at least part of which is disposed coaxially about the mandrel, a sheath assembly including a distal sheath portion and a proximal sheath potion, wherein the distal sheath portion and the proximal sheath portion are configured to constrain the vascular graft against the mandrel in an insertion diameter and a actuator that is moveable relative to the grip and engages the sheath assembly, wherein operation of the actuator causes at least one of the distal sheath portion and the proximal sheath portion to separate longitudinally to free at least a portion of the vascular graft. Further, a vascular graft is expandable from an insertion state to a deployed state and at least two suture cuffs are located between opposed ends of the vascular graft.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 1, 2023
    Assignee: Aquedeon Medical, Inc.
    Inventors: Thomas J. Palermo, Pin-Hsuan Lee, Jimmy Jen
  • Patent number: 11710659
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 11703992
    Abstract: A method of identifying a flange specification based on an augmented reality interface includes steps of: providing a first interface, through which an operator picks real-time images of a flange at different viewing angles, and creating a virtual flange surface according to the real-time images; providing a second interface, through which the operator picks three circumferential points corresponding to the flange, and creating a virtual flange model having a virtual outer diameter; providing a third interface, through which the operator adjusts a virtual pitch circle diameter of the virtual flange model; providing a fourth interface, through which the operator adjusts a virtual thickness of the virtual flange model; providing a fifth interface, through which the operator inputs a count of bolts; and searching a database according to the virtual outer diameter, the virtual pitch circle diameter and the virtual thickness of the virtual flange model to obtain searched results.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: July 18, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chih-Hsing Chu, Mu-Hsuan Lee, Yen-Ru Chen, Shau-Min Chen
  • Patent number: 11702254
    Abstract: A locking mechanism for container and lid thereof may include a container and a lid, and the peripheral edge of the upper opening of the container has a first periphery edge. At least two first coupling portions, which are located at symmetric positions, and at least two second coupling portions, which are located at symmetric positions, outwardly protrude from the first periphery edge respectively. The lid comprises a second peripheral edge at the outer periphery thereof, and the inner surface of the second peripheral edge is configured to couple with and cover the first peripheral edge of the container. At least two first connecting portions respectively protrude from the second peripheral edge at symmetric positions, and at least two second connecting portions, which are located at symmetric positions, outwardly protrude from the second periphery edge respectively.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: July 18, 2023
    Inventor: Chen-Hsuan Lee
  • Patent number: 11697183
    Abstract: A method of forming a CMP pad includes providing a solution of a block copolymer (BCP), where the BCP includes a first segment and a second segment connected to the first segment, the second segment being different from the first segment in composition. The method further includes processing the BCP to form a polymer network having a first phase and a second phase embedded in the first phase, where the first phase includes the first segment and the second phase includes the second segment, and subsequently removing the second phase from the polymer network, thereby forming a polymer film that includes a network of pores embedded in the first phase. Thereafter, the method proceeds to combining the CMP top pad and a CMP sub-pad to form a CMP pad, where the CMP top pad is configured to engage with a workpiece during a CMP process.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Hsuan Lee, Ming-Shiuan She, Chen-Hao Wu, Chun-Hung Liao, Shen-Nan Lee, Teng-Chun Tsai
  • Publication number: 20230215147
    Abstract: A model generating apparatus and method are provided. The apparatus receives a plurality of sample images. The apparatus generates a plurality of adversarial samples corresponding to the sample images. The apparatus inputs the sample images and the adversarial samples respectively to a first encoder and a second encoder in a self-supervised neural network to generate a plurality of first feature extractions and a plurality of second feature extractions. The apparatus calculates a similarity of each of the first feature extractions and the second feature extractions to train the self-supervised neural network. The apparatus generates a task model based on the first encoder and a plurality of labeled data.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 6, 2023
    Inventors: Yung-Hui LI, Ting-Hsuan LEE, Nien-Yi JAN, Wei-Bin LEE, Yen-Cheng LIN
  • Publication number: 20230215761
    Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.
    Type: Application
    Filed: March 6, 2023
    Publication date: July 6, 2023
    Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chia-Ta Yu, Han-Jong Chia
  • Patent number: 11694825
    Abstract: A radial-leaded over-current protection device comprises a PTC element, a first electrode lead, a second electrode lead and an electrically insulating encapsulation layer. The PTC element comprises a first conductive layer, a second conductive layer and a PTC material layer laminated therebetween. The PTC material layer comprises crystalline polymer and conductive filler dispersed therein. The first electrode lead has an end connecting to the first conductive layer, whereas the second electrode lead has an end connecting to the second conductive layer. The electrically insulating encapsulation layer includes a fluorine-containing polymer, and wraps around an entire outer surface of the PTC element and the ends of the first and second electrodes connecting to the PTC element. The electrically insulating encapsulation layer has a thickness of 102˜105 nm, and the radial-leaded over-current protection device has an initial resistance Rbf of 0.0017˜0.0027?.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: July 4, 2023
    Assignee: POLYTRONICS TECHNOLOGY CORP.
    Inventors: Feng Ji Li, Yi-Hsuan Lee, Yung Hsien Chang
  • Patent number: 11688607
    Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Hung Liao, Chung-Wei Hsu, Tsung-Ling Tsai, Chen-Hao Wu, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20230190202
    Abstract: An electrophysiological signal measurement system, an electrophysiological signal adjustment method and an electrode assembly are provided. The electrophysiological signal measurement system includes an electrode assembly, a variation adjustment device and a signal processing device. The electrode assembly receives an electrophysiological signal, a first electrical characteristic value and a second electrical characteristic value. The variation adjustment device includes a comparison unit and a searching unit. The comparison unit receives the first electrical characteristic value and the second electrical characteristic value, and determines whether a difference between the first electrical characteristic value and the second electrical characteristic value is greater than a threshold.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 22, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Heng-Yin CHEN, Yun-Yi HUANG, Min-Hsuan LEE, Yi-Cheng LU, Yu-Chiao TSAI, Bor-Shyh LIN
  • Patent number: 11682675
    Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11682571
    Abstract: Apparatus and methods for handling die carriers are disclosed. In one example, a disclosed apparatus includes: a load port configured to load a die carrier operable to hold a plurality of dies into a processing tool; and a lane changer coupled to the load port and configured to move at least one die in the die carrier to an input of the processing tool and transfer the at least one die into the processing tool for processing the at least one die.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Kai-Chieh Huang, Wei-Ting Hsiao, Yang-Ann Chu, I-Lun Yang, Hsuan Lee
  • Publication number: 20230166891
    Abstract: A locking mechanism for container and lid thereof may include a container and a lid, and the peripheral edge of the upper opening of the container has a first periphery edge. At least two first coupling portions, which are located at symmetric positions, and at least two second coupling portions, which are located at symmetric positions, outwardly protrude from the first periphery edge respectively. The lid comprises a second peripheral edge at the outer periphery thereof, and the inner surface of the second peripheral edge is configured to couple with and cover the first peripheral edge of the container. At least two first connecting portions respectively protrude from the second peripheral edge at symmetric positions, and at least two second connecting portions, which are located at symmetric positions, outwardly protrude from the second periphery edge respectively.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 1, 2023
    Inventor: CHEN-HSUAN LEE
  • Publication number: 20230170234
    Abstract: A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Inventors: Chih-Hung HUANG, Cheng-Lung WU, Zheng-Lin HE, Yang-Ann CHU, Jiun-Rong PAI, Hsuan LEE
  • Patent number: 11663690
    Abstract: A video processing method includes: decoding apart of a bitstream to generate a decoded frame, where the decoded frame is a projection-based frame that includes projection faces in a projection layout; and remapping sample locations of the projection-based frame to locations on the sphere, where a sample location within the projection-based frame is converted into a local sample location within a projection face packed in the projection-based frame; in response to adjustment criteria being met, an adjusted local sample location within the projection face is generated by applying adjustment to at least one coordinate value of the local sample location within the projection face, and the adjusted local sample location within the projection face is remapped to a location on the sphere; and in response to the adjustment criteria not being met, the local sample location within the projection face is remapped to a location on the sphere.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 30, 2023
    Assignee: MEDIATEK INC.
    Inventors: Ya-Hsuan Lee, Jian-Liang Lin