Abstract: A method for forming a photomask includes receiving a mask substrate including a protecting layer and a shielding layer formed thereon, removing portions of the shielding layer to form a patterned shielding layer, and providing a BSE detector to monitor the removing of the portions of the shielding layer. When a difference in BSE intensities obtained from the BSE detector is greater than approximately 30%, the removing of the portions of the shielding layer is stopped. The BSE intensity in following etching loops becomes stable.

Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.

Abstract: The present disclosure provides a photomask, including a plurality of pattern areas, each of the pattern areas is defined by a respective boundary, a first pattern area including a first mask feature, and a training area adjacent to a boundary of the pattern area, the training area comprising a first training feature, wherein the first training feature is comparable to the first mask feature.

Abstract: A method for forming a photomask includes receiving a mask substrate including a protecting layer and a shielding layer formed thereon, removing portions of the shielding layer to form a patterned shielding layer, and providing a BSE detector to monitor the removing of the portions of the shielding layer. When a difference in BSE intensities obtained from the BSE detector is greater than approximately 30%, the removing of the portions of the shielding layer is stopped. The BSE intensity in following etching loops becomes stable.

Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.

Abstract: A method for forming a photomask includes receiving a mask substrate including a protecting layer and a shielding layer formed thereon, removing portions of the shielding layer to form a patterned shielding layer, and providing a BSE detector to monitor the removing of the portions of the shielding layer. When a difference in BSE intensities obtained from the BSE detector is greater than approximately 30%, the removing of the portions of the shielding layer is stopped. The BSE intensity in following etching loops becomes stable.

Abstract: A method of manufacturing a mask includes depositing an end-point layer over a light transmitting substrate, depositing a phase shifter over the end-point layer, depositing a hard mask layer over the phase shifter, and removing a portion of the hard mask layer and a first portion of the phase shifter to expose a portion of the end-point layer. The end-point layer and the light transmitting substrate are transparent to a predetermined wavelength.

Abstract: A method for forming a photomask includes receiving a mask substrate including a protecting layer and a shielding layer formed thereon, removing portions of the shielding layer to form a patterned shielding layer, and providing a BSE detector to monitor the removing of the portions of the shielding layer. When a difference in BSE intensities obtained from the BSE detector is greater than approximately 30%, the removing of the portions of the shielding layer is stopped. The BSE intensity in following etching loops becomes stable.

Abstract: A method of manufacturing a mask includes depositing an end-point layer over a light transmitting substrate, depositing a phase shifter over the end-point layer, depositing a hard mask layer over the phase shifter, and removing a portion of the hard mask layer and a first portion of the phase shifter to expose a portion of the end-point layer. The end-point layer and the light transmitting substrate are transparent to a predetermined wavelength.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: In general, in one aspect, the disclosure describes a flow control hub that includes a scoreboard memory device to maintain flow control status for a plurality of flows. Each of the flows is identified by an associated index. The apparatus also includes an address decoder to receive a flow control message and to determine an associated index based on the address portion. The apparatus further includes an updater to update the flow control status in said memory device based on the received flow control message.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer unit, and a control unit. The memory cache produces an address and data. Included in the write buffer unit are a plurality of data locations coupled to the memory cache. The control unit directs the first data to any of the plurality of data locations.