Abstract: An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.

Abstract: An integrated circuit applied in a deep neural network is disclosed. The integrated circuit comprises at least one processor, a first internal memory, a second internal memory, at least one MAC circuit, a compressor and a decompressor. The processor performs a cuboid convolution over decompression data for each cuboid of an input image fed to any one of multiple convolution layers. The MAC circuit performs multiplication and accumulation operations associated with the cuboid convolution to output a convoluted cuboid. The compressor compresses the convoluted cuboid into one compressed segment and store it in the second internal memory. The decompressor decompresses data from the second internal memory segment by segment to store the decompression data in the first internal memory. The input image is horizontally divided into multiple cuboids with an overlap of at least one row for each channel between any two adjacent cuboids.

Abstract: An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.

Abstract: A data processing method for performing data processing on wireless received data and an associated data processing apparatus are provided, where the data processing method is applied to an electronic device. The data processing method includes the steps of: wirelessly receiving a plurality of packets corresponding to a same set of speech data from another electronic device; and selectively performing error correction operation on at least one of the plurality of packets to obtain the set of speech data, wherein whether to perform the error correction operation is determined according to at least one characteristic of the plurality of packets. More particularly, the error correction operation is selectively performed for at least one scenario of a timing critical scenario and a re-transmission limited scenario.

Abstract: A data processing method for performing data processing on wireless received data and an associated data processing apparatus are provided, where the data processing method is applied to an electronic device. The data processing method includes the steps of: wirelessly receiving a plurality of packets corresponding to a same set of speech data from another electronic device; and selectively performing error correction operation on at least one of the plurality of packets to obtain the set of speech data, wherein whether to perform the error correction operation is determined according to at least one characteristic of the plurality of packets. More particularly, the error correction operation is selectively performed for at least one scenario of a timing critical scenario and a re-transmission limited scenario.