Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first conductive pad, a second conductive pad, a conductive material and a conductive coil. The first and second conductive pads are disposed over and electrically connected to the interconnection structure individually. The conductive material is electrically isolated from the interconnection structure, wherein bottom surfaces of the conductive material, the first conductive pad and the second conductive pad are substantially aligned. The conductive coil is disposed in the interconnection structure and overlapped by the conductive material. A manufacturing method of a semiconductor structure is also provided.

Abstract: A semiconductor structure and a method are provided. The method includes patterning a substrate to form a first fin structure in a first region and a second fin structure in a second region, wherein a first width of the first fin structure is greater than a second width of the second fin structure; forming a protecting layer on the second fin structure; and forming a first oxide layer over the first fin structure and forming a second oxide layer over the protecting layer, wherein a width of the first oxide layer is greater than a width of the second oxide layer.

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, a control layer disposed over the first ILD layer and containing silicon and oxygen, and a resistor wire disposed over the control layer. An oxygen concentration of the control layer is greater than an oxygen concentration of the first ILD layer.

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

Abstract: The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.

Abstract: The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.

Abstract: A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.

Abstract: A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.

Abstract: A display panel driving device is configured to drive a display panel. The display panel driving device includes a driving unit, a digital circuit unit and a selecting unit. The driving unit includes a first channel and a second channel. The first channel includes a first amplifier, and the second channel comprises a second amplifier. The digital circuit unit is coupled to the driving unit, and configured to output a first signal and a second signal to the first channel and the second channel respectively. The selecting unit is coupled to the driving unit. When the first signal and the second signal are the same, the selecting unit optionally switches off the first amplifier or the second amplifier.

Abstract: A digital power meter communication system includes terminal network communication devices, at least one concentrator network communication device and a digital power meter communication device. The digital power meter communication device is electrically connected with the at least one concentrator network communication device. Each of the terminal network communication devices is electrically connected with a terminal digital power meter. The digital power meter communication device includes a storage unit and a processing unit. The storage unit stores pieces of electrical connection information and digital power meter communication programs. The processing unit constructs a virtual tunnel to build connection with the target network communication device through the network.

Abstract: A digital power meter communication system includes terminal network communication devices, at least one concentrator network communication device and a digital power meter communication device. The digital power meter communication device is electrically connected with the at least one concentrator network communication device. Each of the terminal network communication devices is electrically connected with a terminal digital power meter. The digital power meter communication device includes a storage unit and a processing unit. The storage unit stores pieces of electrical connection information and digital power meter communication programs. The processing unit constructs a virtual tunnel to build connection with the target network communication device through the network.

Abstract: A method and a system for network synchronization are provided. In this method, when a node attempts to join a network, a parent node is searched from all other nodes already joined the network per specific time interval. If the parent node can be found, sync-information sent by the parent node is received by the node so as to synchronize with the parent node and enter a working mode. When a sleeping instruction sent by the parent node is received, or a timer determines that a network ending time is reached according to the sync-information, the node switches to a sleeping mode. However, when the timer determines that a network wakeup time is reached according to the sync-information, the node attempts to join the network again. All nodes in the network can work and sleep simultaneously so as to extend the lifetime of the battery.

Abstract: A method and a system for network synchronization are provided. In this method, when a node attempts to join a network, a parent node is searched from all other nodes already joined the network per specific time interval. If the parent node can be found, sync-information sent by the parent node is received by the node so as to synchronize with the parent node and enter a working mode. When a sleeping instruction sent by the parent node is received, or a timer determines that a network ending time is reached according to the sync-information, the node switches to a sleeping mode. However, when the timer determines that a network wakeup time is reached according to the sync-information, the node attempts to join the network again. All nodes in the network can work and sleep simultaneously so as to extend the lifetime of the battery.