Patents by Inventor Hsueh-Te Wang
Hsueh-Te Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10978406Abstract: A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate has a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a patterned conductive layer in a level of the insulating layer. The patterned conductive layer includes conductors in and along the edge region. The edge region is partially exposed from the conductors, as viewed from a top-view perspective. The conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductors.Type: GrantFiled: June 13, 2018Date of Patent: April 13, 2021Assignee: MediaTek Inc.Inventors: Hung-Jen Chang, Jen-Chuan Chen, Hsueh-Te Wang, Wen-Sung Hsu
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Patent number: 10685943Abstract: A semiconductor chip package includes a substrate; a semiconductor die mounted on the substrate, wherein the semiconductor die comprises a bond pad disposed on an active surface of the semiconductor die, and a passivation layer covering perimeter of the bond pad, wherein a bond pad opening in the passivation layer exposes a central area of the bond pad; a conductive paste post printed on the exposed central area of the bond pad; and a bonding wire secured to a top surface of the conductive paste post. The conductive paste post comprises copper paste.Type: GrantFiled: September 12, 2017Date of Patent: June 16, 2020Assignee: MediaTek Inc.Inventors: Shiann-Tsong Tsai, Hsueh-Te Wang
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Publication number: 20190019763Abstract: A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate has a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a patterned conductive layer in a level of the insulating layer. The patterned conductive layer includes conductors in and along the edge region. The edge region is partially exposed from the conductors, as viewed from a top-view perspective. The conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductors.Type: ApplicationFiled: June 13, 2018Publication date: January 17, 2019Inventors: Hung-Jen CHANG, Jen-Chuan CHEN, Hsueh-Te WANG, Wen-Sung HSU
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Patent number: 10037936Abstract: A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting the semiconductor die to the carrier substrate, an insulating material coated on the bonding wires, and a molding compound covering the top surface and encapsulating the semiconductor die, the plurality of bonding wires, and the insulating material.Type: GrantFiled: June 8, 2016Date of Patent: July 31, 2018Assignee: MediaTek Inc.Inventors: Shiann-Tsong Tsai, Hsueh-Te Wang, Chin-Chiang Chang
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Publication number: 20180006002Abstract: A semiconductor chip package includes a substrate; a semiconductor die mounted on the substrate, wherein the semiconductor die comprises a bond pad disposed on an active surface of the semiconductor die, and a passivation layer covering perimeter of the bond pad, wherein a bond pad opening in the passivation layer exposes a central area of the bond pad; a conductive paste post printed on the exposed central area of the bond pad; and a bonding wire secured to a top surface of the conductive paste post. The conductive paste post comprises copper paste.Type: ApplicationFiled: September 12, 2017Publication date: January 4, 2018Inventors: Shiann-Tsong Tsai, Hsueh-Te Wang
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Publication number: 20170125327Abstract: A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting the semiconductor die to the carrier substrate, an insulating material coated on the bonding wires, and a molding compound covering the top surface and encapsulating the semiconductor die, the plurality of bonding wires, and the insulating material.Type: ApplicationFiled: June 8, 2016Publication date: May 4, 2017Inventors: Shiann-Tsong Tsai, Hsueh-Te Wang, Chin-Chiang Chang
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Publication number: 20120119342Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicants: MediaTek Inc., ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng, Hsueh-Te Wang, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Ping-Feng Yang
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Patent number: 7253508Abstract: A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “?”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.Type: GrantFiled: December 17, 2004Date of Patent: August 7, 2007Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chien Liu, Hsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Tai-Yuan Huang
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Patent number: 7164202Abstract: A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.Type: GrantFiled: November 15, 2004Date of Patent: January 16, 2007Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsueh-Te Wang, Meng-Jen Wang, Chien Liu, Chi-Hao Chiu
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Patent number: 7067904Abstract: A flip-chip type quad flat package and a leadframe. The leadframe comprises a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.Type: GrantFiled: November 1, 2004Date of Patent: June 27, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Chien Liu
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Patent number: 7034388Abstract: A stack type flip-chip package is described, including a substrate board, a first chip, a second chip, a packaging material and a heat sink. The substrate board has bump contacts and line contacts thereon, wherein the bump contacts connect with the bonding pads on the active surface of the first chip via bumps. The back surface of the first chip has a redistribution circuit thereon including bump pads and line pads exposed by a passivation layer, wherein the bump pads connect with the bonding pads of the second chip via bumps, and the line pads are connected to the line contacts via conductive wires. The packaging material encloses the first chip and the conductive wires, but may expose the back surface of the second chip, to which a heat sink can be directly bonded.Type: GrantFiled: June 15, 2004Date of Patent: April 25, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chaur-Chin Yang, Hsueh-Te Wang
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Patent number: 7022551Abstract: A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.Type: GrantFiled: October 18, 2004Date of Patent: April 4, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsueh-Te Wang, Meng-Jen Wang, Chien Liu, Chi-Hao Chiu
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Publication number: 20050248037Abstract: A flip-chip package substrate with a high-density layout. A number of pads and a number of traces are formed on an upper surface of the substrate. At least a pad has a short axis and a vertical long axis which are perpendicular to each other. The distance between the elongated pad and the pad adjacent thereto is not smaller than two thirds of the length of the short axis, so that at least two of the traces can pass between the elongated pad and the pad adjacent thereto.Type: ApplicationFiled: May 6, 2005Publication date: November 10, 2005Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Pin Hung, Pao-Nan Li, Hsueh-Te Wang, Yun-Hsiang Tien
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Publication number: 20050156296Abstract: A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.Type: ApplicationFiled: November 15, 2004Publication date: July 21, 2005Inventors: Hsueh-Te Wang, Meng-Jen Wang, Chien Liu, Chi-Hao Chiu
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Publication number: 20050133896Abstract: A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “?”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.Type: ApplicationFiled: December 17, 2004Publication date: June 23, 2005Inventors: Chien Liu, Hsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Tai-Yuan Huang
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Publication number: 20050104167Abstract: A flip-chip type quad flat package and a leadframe. The leadframe comprsies a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.Type: ApplicationFiled: November 1, 2004Publication date: May 19, 2005Inventors: Hsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Chien Liu
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Publication number: 20050101053Abstract: A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.Type: ApplicationFiled: October 18, 2004Publication date: May 12, 2005Inventors: Hsueh-Te Wang, Meng-Jen Wang, Chien Liu, Chi-Hao Chiu
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Publication number: 20040251531Abstract: A stack type flip-chip package is described, including a substrate board, a first chip, a second chip, a packaging material and a heat sink. The substrate board has bump contacts and line contacts thereon, wherein the bump contacts connect with the bonding pads on the active surface of the first chip via bumps. The back surface of the first chip has a redistribution circuit thereon including bump pads and line pads exposed by a passivation layer, wherein the bump pads connect with the bonding pads of the second chip via bumps, and the line pads are connected to the line contacts via conductive wires. The packaging material encloses the first chip and the conductive wires, but may expose the back surface of the second chip, to which a heat sink can be directly bonded.Type: ApplicationFiled: June 15, 2004Publication date: December 16, 2004Inventors: Chaur-Chin Yang, Hsueh-Te Wang
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Patent number: 6768190Abstract: A stack type flip-chip package that utilizes a redistribution circuit on the back of a chip to serve as a bridge for connecting with other chips. The package includes at least a substrate, a first chip, a second chip, some underfill material and some packaging material. The substrate has a plurality of bump contacts and a plurality of line contacts thereon. The first chip has an active surface with a plurality of first bonding pads thereon. The back surface of the first chip has a redistribution circuit. The redistribution circuit has a plurality of bump pads and a plurality of line pads thereon. The second chip has an active surface with a plurality of second bonding pads thereon. Bumps are positioned between the bump contacts and the first bonding pads and between the bump pads and the second bonding pads. Conductive wires connect the line contacts and the line pads. The underfill material fills the space between the chip and the substrate and the gap between the first and the second chips.Type: GrantFiled: April 23, 2002Date of Patent: July 27, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chaur-Chin Yang, Hsueh-Te Wang
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Publication number: 20040124541Abstract: A flip chip package mainly includes a semiconductor chip disposed in a recessed cavity defined in an upper surface of a substrate by flip chip bonding. The lower surface of the substrate is provided with a reinforcement-containing insulating layer thereby enhancing mechanical strength thereof. The upper surface of the substrate is provided with a plurality of solder pads formed at the periphery of the recessed cavity for making external electrical connections. The substrate includes a plurality of chip contact pads provided on the surface of the reinforcement-containing insulating layer and exposed from the recessed cavity wherein the chip contact pads are electrically connected to the solder pads through a plurality of conductive traces.Type: ApplicationFiled: October 8, 2003Publication date: July 1, 2004Inventors: Sung Mao Wu, Hsueh Te Wang, Chi Pin Hung