Patents by Inventor Hsun-An Lee

Hsun-An Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170211
    Abstract: A metal electrode of a ceramic capacitor and a method of forming the same are provided. The method includes mixing metal powders and a barium titanate organic-precursor to obtain precursor powders; adding an adhesive to the precursor powders to obtain a metal slurry; performing a molding process to the metal slurry to obtain a film material; performing a binder burn-out process to the film material to obtain a degumming film; and performing a sintering process to the degumming film to obtain the metal electrode. By mixing specific amount of barium titanate organic-precursor with the metal powders, the barium titanate metallic organic-precursor can be transformed to barium titanate in the following process, and barium titanate can be dispersed between the metals homogeneously. Therefore, electrode continuity can be increased.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 23, 2024
    Inventors: Hsing-I HSIANG, Fu-Su YEN, Chi-Yuen HUANG, Chun-Te LEE, Kai-Hsun YANG, Shih-Ming WANG
  • Publication number: 20240158956
    Abstract: A manufacturing method of a fiber includes: mixing and stirring a plurality of raw materials, to form a mixed liquid, where the plurality of raw materials includes dry copper nanopowder with a particle size not more than 48 nm, a fiber slurry, and an additive; drying the mixed liquid, to remove moisture of the mixed liquid and form a processed raw material; heating the processed raw material, to make the processed raw material be in a semi-molten state; electrifying the processed raw material in the semi-molten state, and then extruding at least one fibril from the processed raw material in the semi-molten state; stretching the at least one fibril; and performing cooling and shaping on at least one stretched fibril, to form a final fiber product.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventor: Hsing-Hsun LEE
  • Patent number: 11984375
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 11982936
    Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang Lee, Ping-Hsun Lin, Yen-Cheng Ho, Chih-Cheng Lin, Chia-Jen Chen
  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240133745
    Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: Chein-Hsun WANG, Ming LE, Tung-Yang LEE, Yu-Chih LIANG, Wen-Chie HUANG, Chen-Tang HUANG, Jenping KU
  • Publication number: 20240136946
    Abstract: This patent presents a multidimensional space vector modulation (MDSVM) circuit formed by coupling a half-bridge logic control circuit not directly coupled to electronic components with at least three half-bridge logic control circuits coupled to electronic components. The half-bridge logic control circuit not directly coupled with any electronic components can form a full-bridge circuit with any other half-bridge logic control circuit coupled with electronic components. Therefore, users can further control the voltage difference between both ends of each electronic component separately and then individually control the strength and direction of current flowing through each electronic component and solving the problem of control attributed to the complexity of prior art.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 25, 2024
    Applicant: TENSOR TECH CO., LTD
    Inventors: Shang Jung LEE, Po-Hsun YEN, Yung-Cheng CHANG, Sung-Liang HOU
  • Publication number: 20240131819
    Abstract: A thermally conductive board includes a first metal layer, a second metal layer, and a thermally conductive layer. The material of the first metal layer includes copper, and the first metal layer has a first top surface and a first bottom surface opposite to the first top surface. A first metal coating layer covers the first bottom surface. The material of the second metal layer includes copper, and the second metal layer has a second top surface and a second bottom surface opposite to the second top surface. A second metal coating layer covers the second top surface and faces the first metal coating layer. The thermally conductive layer is an electrically insulator laminated between the first metal coating layer and the second metal coating layer.
    Type: Application
    Filed: May 3, 2023
    Publication date: April 25, 2024
    Inventors: KAI-WEI LO, WEN-FENG LEE, HSIANG-YUN YANG, KUO-HSUN CHEN
  • Patent number: 11967446
    Abstract: An inductor is disclosed, the inductor comprising: a T-shaped magnetic core, being made of a material comprising an annealed soft magnetic metal material and having a base and a pillar integrally formed with the base, wherein ?CĂ—Hsat?1800, where ?C is a permeability of the T-shaped magnetic core, and Hsat (Oe) is a strength of the magnetic field at 80% of ?C0, where ?C0 is the permeability of the T-shaped magnetic core when the strength of the magnetic field is 0.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: April 23, 2024
    Assignee: CYNTEC CO., LTD.
    Inventors: Chun-Tiao Liu, Lan-Chin Hsieh, Tsung-Chan Wu, Chi-Hsun Lee, Chih-Siang Chuang
  • Patent number: 11965270
    Abstract: A deodorant and antibacterial copper nanofiber yarn and a manufacturing method thereof are provided, the manufacturing method including: providing a raw material, including a polyblend slurry, a nano-metal solution, a plurality of inorganic particles, and a plurality of TPU rubber particles; stirring the raw material into a mixed material; making second metal contact the first metal ion fiber to cause the first metal ion to undergo a reduction reaction to obtain a first metal nanoparticle; drying the mixed material; performing hot-melt spinning on the mixed material, the plurality of TPU rubber particles, after being hot-melted, being coated on an outer peripheral side of the spun wire to form a first-phase wire; forcibly cooling the first-phase wire; stretching the first-phase wire; air-cooling the first-phase wire to form a second-phase wire; and collecting the second-phase wire to make the wire into a finished deodorant and antibacterial copper nanofiber yarn.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 23, 2024
    Assignee: QUANN CHENG INTERNATIONAL CO., LTD.
    Inventor: Hsing Hsun Lee
  • Publication number: 20240128232
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Patent number: 11961777
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11961938
    Abstract: A method of processing light-emitting elements includes: transferring a plurality of light-emitting elements from original wafers or next-stage carriers, based on a predetermined pattern. The predetermined pattern arranges two adjacent LED groups in a first direction on the original wafer or carriers to be placed on two non-adjacent positions in the first direction on the next-stage carriers. The light-emitting elements on the original wafer have a horizontal wafer pitch and a vertical wafer pitch. The light-emitting elements on each of the next-stage carriers have a first horizontal pitch and a first vertical pitch. The first horizontal pitch is greater than the horizontal wafer pitch, or the first vertical pitch is greater than the vertical wafer pitch. Besides, a light-emitting element device using the aforementioned method is also provided.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 16, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Chang-Lin Lee
  • Patent number: 11946170
    Abstract: A method for manufacturing a deodorant and antibacterial protective cloth includes: providing a first fiber thread and a second fiber thread, where the first fiber thread is a core-spun yarn formed by a blended slurry, a nano metal solution, a plurality of inorganic particles, and a plurality of thermoplastic polyurethane colloidal particles, the thermoplastic polyurethane colloidal particles are hot melted and then wrapped around a peripheral side of a core thread of the core-spun yarn for isolation from an outer wrapping layer of the core-spun yarn, and the second fiber thread is the same as the first fiber thread or is a single-thread yarn formed by the blended slurry and the nano metal solution; and intersecting and laminating the first fiber thread and the second fiber thread to form a plurality of bonding layers.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 2, 2024
    Assignee: QUANN CHENG INTERNATIONAL CO., LTD.
    Inventor: Hsing-Hsun Lee
  • Publication number: 20240107666
    Abstract: A circuit board includes a first electronic component and a circuit substrate. The first electrode component includes two electrodes. The circuit substrate includes an inner substrate and an outer substrate formed on the inner substrate. The inner substrate defines a receiving cavity, and the first electronic component received in the receiving cavity. Each electrode faces an inner sidewall of the receiving cavity. The inner substrate includes a first insulating layer and a blocking layer embedded in the first insulating layer, an end of the blocking layer exposed from the inner sidewall. The outer substrate defines two through holes. Each through hole passes through a portion of the first insulating layer connected to the inner sidewall and exposes the blocking layer. A top end of each of the two electrodes facing the outer substrate is partially received in one through hole.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 28, 2024
    Inventors: MING-HSUN LEE, CHEN-EN LIN
  • Publication number: 20240105631
    Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Inventors: Jeng-An Wang, Sheng-Chi Lin, Hao-Cheng Hou, Tsung-Ding Wang, Chien-Hsun Lee
  • Publication number: 20240094625
    Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Chih-Cheng LIN, Chia-Jen CHEN
  • Publication number: 20240096812
    Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Lee
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang