Patents by Inventor Hua Hsu
Hua Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194646Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.Type: ApplicationFiled: September 29, 2023Publication date: June 13, 2024Inventors: Chin-Tang Hsieh, Lung-Hua Ho, Chih-Ming Kuo, Chen-Yu Wang, Chih-Hao Chiang, Pai-Sheng Cheng, Kung-An Lin, Chun-Ting Kuo, Yu-Hui Hu, Wen-Cheng Hsu
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Publication number: 20240192597Abstract: A polymer is formed by a reaction of phenolic epoxy resin or bisphenol epoxy resin and carboxylic acid, wherein the phenolic epoxy resin has a chemical structure of wherein W is H, alkyl group, or halogen. R1 is methylene, methylene diphenyl, dimethylene benzene, tetrahydrodicyclopentadiene, or n=1 to 8. The bisphenol epoxy resin has a chemical structure of wherein Z is H or alkyl group; R4 is methylene, methylmethylene, dimethylmethylene, ethylmethylmethylene, bi(trifluoromethyl)methylene, fluorenylidene, or sulfonyl group; and p=1 to 10. The carboxylic acid has a chemical structure of HOOC—Ar—(—X)m, HOOC—R2, or a combination thereof, wherein Ar is benzene or naphthalene; X is hydroxy group, alkoxy group, or alkyl group, and at least one X is hydroxy group; m=1 to 3, wherein R2 is C3-7 alkyl group.Type: ApplicationFiled: October 25, 2023Publication date: June 13, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Ying HSU, Yao-Jheng HUANG, Ming-Tzung WU, Chin-Hua CHANG, Te-Yi CHANG
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Publication number: 20240192456Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: ApplicationFiled: February 26, 2024Publication date: June 13, 2024Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240182141Abstract: A multihull module is provided. The multihull module includes multiple power floats, an actuation interface controller, and a vehicle controller. The power floats are disposed on a vehicle. The actuation interface controller is coupled to the power floats, and is configured to control the power floats. The vehicle controller is coupled to the actuation interface controller, and is configured to provide a control signal to the actuation interface controller. The actuation interface controller controls the power floats according to the control signal.Type: ApplicationFiled: December 6, 2022Publication date: June 6, 2024Applicant: Metal Industries Research & Development CentreInventors: Kuang-Shine Yang, Chao Chieh Hsu, Ping-Hua Su, Tsung-Yi Lan, Chia-Yu Hung
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Publication number: 20240182144Abstract: A ship docking system and a ship docking method are provided. The ship docking system includes a computing device, an unmanned aerial vehicle communicating wirelessly with the computing device and pre-docked on a charging platform, and a display device communicating wirelessly with the computing device. When the computing device determines that the ship is performing a port entry operation, the computing device controls the unmanned aerial vehicle to move to a preset height above the ship and to obtain a panoramic image of the ship. The unmanned aerial vehicle transmits the panoramic image to the computing device, so that the computing device analyzes the panoramic image to perform a collision prediction of the ship, and transmits a collision prediction result to the display device.Type: ApplicationFiled: December 5, 2022Publication date: June 6, 2024Applicant: Metal Industries Research & Development CentreInventors: Kuang-Shine Yang, Ping-Hua Su, Chao Chieh Hsu
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Publication number: 20240182651Abstract: Provided is a hydrogel composition, which comprises a modified HA, PEGDA and water; wherein, based on a total weight of the hydrogel composition, a content of the modified HA is 1 wt % to 7 wt % and a content of PEGDA is 43 wt % to 49 wt %; the modified HA is obtained by modifying HA with methacrylic anhydride; an average molecular weight of PEGDA is 1 kDa to 10 kDa. The hydrogel composition of the present invention has good compatibility of raw materials, which does not cause HA precipitation, and a hydrogel material produced therefrom simultaneously has good mechanical properties, good swell capability and good biocompatibility, such that the hydrogel material can be applied in many fields.Type: ApplicationFiled: February 14, 2023Publication date: June 6, 2024Inventors: Ta-Jo LIU, Hsiu-Feng YEH, Shin-Yi YIN, Yi-Jyun LIAO, Ying-Hua HSU
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Patent number: 11996466Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.Type: GrantFiled: May 9, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
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Publication number: 20240172456Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.Type: ApplicationFiled: January 23, 2024Publication date: May 23, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
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Publication number: 20240163785Abstract: A method for performing wireless communication in MLO architecture is applicable to an AP MLD connected with a non-AP MLD through multiple links. The multiple links include at least a first link and a second link, the non-AP MLD operates in ML-SMPS mode. The method includes transmitting an initial control frame to the non-AP MLD via the first link, to trigger at least one link of the multiple links to be activated at the non-AP MLD to support a reception with respective negotiated number of spatial streams, receiving a response frame via the first link in response to the transmission of the initial control frame, and initiating frame exchange between the AP MLD and the non-AP MLD via a target link of the at least one link. The target link is selected from the at least one link according to the response frame. The first link is a primary link.Type: ApplicationFiled: October 31, 2023Publication date: May 16, 2024Applicant: MEDIATEK INC.Inventors: Hao-Hua Kang, Cheng-Ying Wu, Chien-Fang Hsu, Chih-Chun Kuo
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Patent number: 11983680Abstract: An intelligent monitoring system for waste disposal and the method thereof are provided, which include a plurality of operational devices and stages. First, a transportation stage is performed to loading a transport vehicle with a waste so as to transport the waste to a disposal station for further treatment. A camera and a sensor for detecting abnormal conditions are installed any one of the operational devices or installed in the operational path of any one of the operational devices. The camera records the videos of the operational stages, captures the images from the videos and recognizes the images in order to determine whether the abnormal conditions occur in any one of the operational stages. Alternatively, the camera is triggered to capture the images and recognize the images after the abnormal conditions are detected by the sensor in order to determine whether the abnormal conditions actually occur.Type: GrantFiled: June 12, 2021Date of Patent: May 14, 2024Assignee: CHASE SUSTAINABILITY TECHNOLOGY CO., LTD.Inventors: Yung-Fa Yang, Tsung-Tien Chen, Shao-Hsin Hsu, Bo-Wei Chen, Chia-Ching Chen, Ming-Hua Tang
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Publication number: 20240153840Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
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Publication number: 20240147606Abstract: An electronic device includes a first substrate structure, multiple electronic elements and a second substrate structure. The first substrate structure includes a first substrate. The electronic elements are disposed on the first substrate. The second substrate structure is coupled to the first substrate structure. The second substrate structure includes a second substrate, a protection circuit, a driving circuit and a bonding pad. The protection circuit is disposed on the second substrate. The driving circuit is disposed on the second substrate and configured to drive at least a part of the electronic elements. The bonding pad is disposed on the second substrate. The protection circuit is respectively coupled to the bonding pad and the driving circuit. The electronic device may reduce the damage caused by electrostatic discharge or reduce the impact of the bonding process of the bonding pad on signal conduction.Type: ApplicationFiled: September 14, 2023Publication date: May 2, 2024Applicant: Innolux CorporationInventors: Mu-Fan Chang, Yi-Hua Hsu, Hung-Sheng Liao, Min-Hsin Lo, Ming-Chun Tseng, Ker-Yih Kao
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Patent number: 11974479Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.Type: GrantFiled: December 11, 2020Date of Patent: April 30, 2024Assignee: INNOLUX CORPORATIONInventors: Shun-Yuan Hu, Chin-Lung Ting, Li-Wei Mao, Ming-Chun Tseng, Kung-Chen Kuo, Yi-Hua Hsu, Ker-Yih Kao
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Patent number: 11969448Abstract: A probiotic composition for improving an effect of a chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is disclosed in the present disclosure. The probiotic composition comprises an effective amount of Lactobacillus paracasei GMNL-133, an effective amount of Lactobacillus reuteri GMNL-89, and a pharmaceutically acceptable carrier, wherein the Lactobacillus paracasei GMNL-133 was deposited in the China Center for Type Culture Collection on Sep. 26, 2011 under an accession number CCTCC NO. M 2011331, and the Lactobacillus reuteri GMNL-89 was deposited in the China Center for Type Culture Collection on Nov. 19, 2007 under an accession number CCTCC NO. M 207154. A method for improving the effect of the chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is further disclosed in the present disclosure.Type: GrantFiled: May 12, 2021Date of Patent: April 30, 2024Assignee: GENMONT BIOTECH INC.Inventors: Wan-Hua Tsai, I-ling Hsu, Shan-ju Hsu, Wen-ling Yeh, Ming-shiou Jan, Wee-wei Chieng, Li-jin Hsu, Ying-chun Lai
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Patent number: 11973001Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.Type: GrantFiled: May 5, 2023Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Shen Yeh, Chin-Hua Wang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng
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Publication number: 20240136280Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
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Publication number: 20240130246Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
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Organometallic complex, catalyst composition employing the same, and method for preparing polyolefin
Patent number: 11958929Abstract: An organometallic complex, a catalyst composition employing the same, and a method for preparing polyolefin are provided. The organometallic compound has a structure represented by Formula (I) wherein M is Ti, Zr, or Hf; X is —O—, or —NR6—; R1 and R2 are independently hydrogen, C1-6 alkyl group, C6-12 aryl group, or R1 and R2 are combined with the carbon atoms, to which they are attached, to form an C6-12 aryl moiety; R3, R4 and R5 are independently fluoride, chloride, bromide, C1-6 alkyl group, C6-12 aryl group, C3-6 hetero aryl group, C7-13 aryl alkyl group or C7-12 alkyl aryl group; and R6 is hydrogen, C6-12 aryl group or C7-12 alkyl aryl group.Type: GrantFiled: June 24, 2022Date of Patent: April 16, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Wei Hsu, Jyun-Wei Hong, Pao Tsern Lin, Shu-Hua Chan -
Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11956972Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.Type: GrantFiled: April 13, 2021Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Si-Han Tsai, Ching-Hua Hsu, Chen-Yi Weng, Po-Kai Hsu