Abstract: A manufacturing method of a tiling electronic device includes the following steps. A first electronic panel is provided. The first electronic panel includes multiple first bumps and multiple first conducting lines, and the first bumps and the first conducting lines are disposed on a side surface of the first electronic panel. A second electronic panel is provided. The second electronic panel includes multiple second bumps and multiple second conducting lines, and the second bumps and the second conducting lines are disposed on a side surface of the second electronic panel. The first electronic panel and the second electronic panel are coupled through the first bumps and the second bumps. Multiple conducting elements are formed, so that the first conducting lines are electrically connected with the second conducting lines through the conducting elements after the first electronic panel and the second electronic panel are coupled.

Abstract: A circuit board assembly with a fully embedded photosensitive chip which does not require an increase in board width for the re-routing of wires around the photosensitive chip includes a circuit board and a reinforced plate at a lower elevation which is connected to the circuit board. The circuit board defines a through hole and a plurality of conductive lines. The conductive lines or the portion of them which are cut off by the location of the through hole accommodating the chip are repeated by connecting lines carried on the reinforced plate, the plurality of connecting lines connects to and continues the conductive lines which are cut off by the hole.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A headband device is provided. The headband device includes a first knob, a first transmission mechanism, a vertical adjustment mechanism and a vertical headband. The first knob is rotated around a first axis. The first transmission mechanism is connected to the first knob, wherein the first transmission mechanism is rotated by the first knob around a second axis, wherein the first axis is perpendicular to the second axis. The vertical adjustment mechanism is adapted to be connected to the first transmission mechanism, wherein the vertical adjustment mechanism is rotated by the first transmission mechanism and is rotated around the second axis. The vertical headband is connected to the vertical adjustment mechanism, wherein the vertical headband is moved by the vertical adjustment mechanism and the tightness of the vertical headband is adjustable.

Abstract: Embodiments of the present disclosure provide techniques for determining synchronization signal (SS)/physical broadcast channel (PBCH) block (SSB)-based measurement timing configuration (SMTC) for measurement objects for which a user equipment is to measure feedback information in one or more measurement gaps. Other embodiments may be described and claimed.

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

Abstract: In one example, an electronic device housing may include a first cover, a second cover, and a latch assembly to detachably connect the first cover and the second cover. The latch assembly may include a first bracket to fixedly engage with the first cover, a latch to slide back and forth along the first bracket between a lock position to hold the second cover and an unlock position to release the second cover, an elastic member disposed between the latch and the first bracket to generate a force to the latch to hold the second cover, and a cable connected to the latch. The cable may generate a pulling force to the latch to release the second cover when an external force is applied to the cable.

Abstract: A laparoscopic image smoke removal method based on a generative adversarial network, and belongs to the technical field of computer vision. The method includes: processing a laparoscopic image sample to be processed using a smoke mask segmentation network to acquire a smoke mask image; inputting the laparoscopic image sample to be processed and the smoke mask image into a smoke removal network, and extracting features of the laparoscopic image sample to be processed using a multi-level smoke feature extractor to acquire a light smoke feature vector and a heavy smoke feature vector; and acquiring, according to the light smoke feature vector, the heavy smoke feature vector and the smoke mask image, a smoke-free laparoscopic image by filtering out smoke information and maintaining a laparoscopic image by using a mask shielding effect. The method has the technical effects of robustness and ability of being embedded into a laparoscopic device for use.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: A light emitting keyboard includes a frame having a translucent frame body, a plurality of key modules each having a keycap, and a backlight module including a light source circuit board, a first light guide plate disposed on top of the light source circuit board, a second light guide plate disposed under the light source circuit board, a plurality of first light-emitting members extending upwardly through the first light guide plate, a plurality of second light-emitting members extending downwardly through the second light guide plate, and a reflector plate disposed under the second light guide plate. Light emitted from the first light-emitting members is transmitted in the first light guide plate and projects upwardly onto the keycaps. Light emitted from the second light-emitting members is transmitted in the second light guide plate is reflected by the reflector plate, and projects onto the frame body.

Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.

Abstract: The present invention relates to a hexatoxin peptide variant comprising a. an amino acid sequence which is at least 90% identical to any one of SEQ ID NOs: 27 to 29, wherein the amino acid sequence has at least one amino acid variant on position N27; b. an amino acid sequence which is at least 90% identical to any one of SEQ ID NOs: 2, 6, 7, 30 or 32, wherein the amino acid sequence has at least one amino acid variant on position N28; c. an amino acid sequence which is at least 90% identical to any one of SEQ ID NOs: 1, 3, 4, 5, 8 to 24 or 31, wherein the amino acid sequence has at least one amino acid variant on position N29; d. an amino acid sequence which is at least 90% identical to SEQ ID NO: 25, wherein the amino acid sequence has at least one amino acid variant on position N30; e. an amino acid sequence which is at least 90% identical to SEQ ID NOs: 26, wherein the amino acid sequence has at least one amino acid variant on position N31; or f.

Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.

Abstract: Apparatus, systems and methods for irrigating lands are disclosed. In one example, an irrigation system is disclosed. The irrigation system includes a gate and a microcontroller unit (MCU). The gate is configured for adjusting a water flow for irrigating a piece of land. The MCU is configured for controlling the gate to adjust the water flow based on environmental information related to the piece of land.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.